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High-precision time delay system and method based on FPGA and time delay chip

A delay chip and delay system technology, which is applied in general control systems, control/regulation systems, delayed output pulse operations, etc., can solve problems such as large ramp noise, small delay range, and uneven step delay , to achieve the effects of large delay range, high delay resolution, and strong signal anti-interference ability

Pending Publication Date: 2021-03-02
ZHONGBEI UNIV
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Problems solved by technology

[0003] Aiming at the technical problems of the above-mentioned double-ramp wave comparison method with uneven step delay, relatively large noise of the ramp itself, and relatively small delay range, the present invention provides a device with high delay accuracy, large delay range, and strong anti-interference ability. High-precision delay system and method based on FPGA and delay chip

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Embodiment Construction

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0030] A high-precision delay system based on FPGA and delay chip, including external trigger input module U1, FPGA module U2, low-jitter clock module U3, fine delay generation module U4, ultra-narrow pulse width signal generation module U5, external trigger The input module U1 is connected to the I / O port of the FPGA module U2. The FPGA module U2 is connected to the low-jitter clock module U3. The low-jitter clock module U3 provides a low-jitter clock signal f...

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Abstract

The invention belongs to the technical field of high-precision time delay, and particularly relates to a high-precision time delay system and method based on an FPGA and a time delay chip, and the system comprises an external triggering input module, an FPGA module, a low-jitter clock module, a fine time delay generation module, and an ultra-narrow pulse width signal generation module. The external triggering input module is connected with an I / O port of the FPGA module. The FPGA module is connected with a low-jitter clock module, the low-jitter clock module U3 provides a low-jitter clock signal for the FPGA module, the FPGA module is connected with the fine delay generation module, and the fine delay generation module is connected to the ultra-narrow pulse width signal generation module.Coarse time delay is achieved through counting of the FPGA module, and the time delay range is large; the fine time delay generation module can realize fine time delay through a special time delay chip, and the time delay resolution is high and can reach a time delay range of 5 ps to 5.115 ns; and the low-jitter clock module is adopted to generate low-jitter clock signals, and low-jitter and high-quality reference clock signals are provided for the FPGA. The system and the method are used for signal delay.

Description

technical field [0001] The invention belongs to the technical field of high-precision time-delay, and in particular relates to a high-precision time-delay system and method based on an FPGA and a time-delay chip. Background technique [0002] The delay circuit in the prior art may have problems such as low delay accuracy or insufficient delay range. For example, although the dual-ramp comparison method can achieve a delay accuracy of 8.6ps, it has problems such as uneven step delay and relatively large noise of the ramp itself. The dedicated delay chip can achieve a delay accuracy of less than 10 ps, ​​but the delay range is relatively small, and it is also not enough for the sampler to sample high-frequency signals of 25 GHz and above. Contents of the invention [0003] Aiming at the technical problems of the above-mentioned double-ramp wave comparison method with uneven step delay, relatively large noise of the ramp itself, and relatively small delay range, the present ...

Claims

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Application Information

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IPC IPC(8): H03K5/135H03K5/00G05B19/042
CPCH03K5/135H03K5/00G05B19/042H03K2005/00156H03K2005/00163H03K2005/00293
Inventor 刘震张敏娟王志斌姚鑫凯李春阳苗宛茹
Owner ZHONGBEI UNIV
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