High-precision clock synchronization method based on FPGA

Abstract

The invention discloses a high-precision clock synchronization method based on an FPGA. The method comprises the following steps: acquiring a recovery clock synchronous with the frequency of a main node; carrying out the frequency multiplication processing through FPGA internal logic to generate a data sending clock and a system clock; generating a DDMTD clock through recovery clock and FPGA internal clock logic, so that the phase of a timestamp when a data packet is received is determined according to the phase difference between a system clock and the DDMTD clock, and clock synchronization is achieved. According to the method, high-precision clock synchronization nodes are realized by using FPGA internal resources and are packaged into an FPGA module (IP core), a clock synchronization function can be realized without an additional circuit, and the design of a WR node is greatly simplified.

Description

technical field [0001] The invention relates to the technical field of clock synchronization network, in particular to an FPGA-based high-precision clock synchronization method. Background technique [0002] The clock signal is the basis of sequential logic. It is used to determine when the state in the logic unit is updated. It is a semaphore with a fixed period and has nothing to do with operation. In digital circuits, the clock signal is basically a square wave, and the rising or falling edge of the square wave is often used as the trigger of the circuit action. For distributed digital systems or in time-sensitive large-scale distributed equipment, each node has its own clock signal, and there is a certain deviation between the clocks of each node in the initial state, often requiring high-precision clock synchronization network technology , the system can have a relatively unified clock after synchronization. The performance of clock synchronization determines the time...

AI Technical Summary

Problems solved by technology

The first method requires the user node to reserve a certain interface to connect to the end node of the clock network, and the equipment of the distributed node end system needs to have a corresponding mechanical structure to match it, which will add additional volume to the user node ; The second method requires adding a series of peripheral circuits in the distributed circuit design, and at the same time integrating functions in the code, which increases additional R&D and debugging costs

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