Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

System-level integrated circuit DC voltage drop parallel analysis method and system

An integrated circuit and DC voltage drop technology, applied in CAD circuit design, special data processing applications, design optimization/simulation, etc., can solve problems such as huge memory, CPU time, and high time cost

Active Publication Date: 2021-01-29
北京智芯仿真科技有限公司
View PDF5 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For system-level VLSI with multi-scale structure, if high-quality meshing is directly performed on the area where the entire system-level VLSI is located, the number of grid nodes generated will reach tens of millions or even hundreds of millions. It is difficult to directly solve the tens of millions or even hundreds of millions of finite element sparse matrices formed by the grid. Even if it can be solved, it will require huge memory and CPU time. For the design of system-level VLSI Said that the time cost is too high, so how to provide a high-precision and speed-block solution method to quickly and accurately analyze the DC voltage drop of the system-level VLSI has become an urgent technical problem to be solved

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • System-level integrated circuit DC voltage drop parallel analysis method and system
  • System-level integrated circuit DC voltage drop parallel analysis method and system
  • System-level integrated circuit DC voltage drop parallel analysis method and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0065] The purpose of the present invention is to provide a parallel analysis method and system for DC voltage drop of system-level integrated circuits, so as to realize fast and accurate analysis of DC voltage drop of system-level VLSI.

[0066] In order to make the above objects, features and advantages of the present invention more comprehensible, the invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0067] In order to solve the above problems, the present invention proposes a parallel analysis method for DC voltage drop of a system-level integrated circuit as a method for quickly and accurately analyzing the DC voltage drop of a system-level VLSI in combination with a delta-star transformation. The complex integrated circuit layout with a scale ranging from centimeters to nanometers is meshed. For field-based problems, the finite element stiffness matrix is ​​written using the finite element method....

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a system-level integrated circuit DC voltage drop parallel analysis method and system, and the method comprises the steps of carrying out the parallel analysis through employing a plurality of coarse particles according to the random dynamic distribution and applying a first distribution principle; enabling each coarse particle to independently and synchronously divide thesystem-level integrated circuit into a plurality of same subsystems by taking a layer as a unit, performing the same mesh generation on the whole system-level integrated circuit and establishing the same finite element sparse matrix; when each subsystem is processed, enabling each coarse particle to process different subsystems, combining other subsystems except the subsystem into a to-be-processed system, eliminating internal nodes of the to-be-processed system by repeatedly utilizing star triangle transformation, and obtaining and solving a finite element sparse matrix only containing a field domain of the subsystem. The invention greatly simplifies the solving process, improves the solving speed on the basis of guaranteeing the solving precision, and achieves the quick and accurate analysis of the DC voltage drop of a system-level super-large-scale integrated circuit.

Description

technical field [0001] The invention relates to the technical field of system-level integrated circuit analysis, in particular to a parallel analysis method and system for system-level integrated circuit DC voltage drop. Background technique [0002] The DC voltage drop analysis of system-level VLSI is an important task in the back-end verification of integrated circuits. In the design process of the current system-level VLSI, the core power supply voltage of the devices in the integrated circuit continues to decrease, and the tolerance of the allowable voltage is getting smaller and smaller, but the operating current and wiring density of the integrated circuit are getting larger and larger. As a result, the DC voltage drop problem has become increasingly prominent. If the DC voltage drop problem is not considered in the design process of the system-level VLSI, it is likely that the noise margin of the system will decrease due to the DC voltage drop problem, and a small di...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/33G06F30/23
CPCG06F30/23G06F30/33
Inventor 唐章宏邹军王芬黄承清汲亚飞
Owner 北京智芯仿真科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products