Shifting register and driving method thereof, grid driving circuit, display panel and device

Abstract

The invention discloses a shift register and a driving method thereof, a gate driving circuit, a display panel and a device. The shift register comprises a first power supply signal input end, a second power supply signal input end, a first signal output end, a first node control module, a first output module, a first voltage stabilizing module and a first clock signal end; the first end of the first voltage stabilizing module is electrically connected with the output end of the first node control module at a first node, the second end of the first voltage stabilizing module is electrically connected with the first control end of the first output module at a second node, and the control end of the first voltage stabilizing module is electrically connected with a first clock signal end; andin the high-frequency display stage, and the first voltage stabilization control module is conducted, and in the low-frequency display stage, the first voltage stabilization control module is conducted or cut off. By additionally arranging the first voltage stabilizing module and the first clock signal end, due to the fact that the leakage current of the first voltage stabilizing module is small,the leakage current of the second node can be reduced in the low-frequency display stage, and stable output of the first signal output end is maintained.

Description

technical field [0001] Embodiments of the present invention relate to the field of display technology, and in particular to a shift register and a driving method, a gate driving circuit, a display panel and a device. Background technique [0002] With the development of display technology, while pursuing a higher resolution of the display device, the power consumption of the display device increases accordingly. In order to reduce power consumption of a display device, a frame rate may be reduced to drive pixels at a low speed during a certain period of time. For example, in a mobile terminal, the normal display mode executes a normal driving frequency based on 60 Hz or 120 Hz; in the standby mode, executes a driving frequency based on 1 Hz-5 Hz, thus reducing power consumption. [0003] In the prior art, a P-type Metal Oxide Semiconductor Field Effect Transistor (Positive Channel Metal Oxide Semiconductor, PMOS) design is mostly used in the shift register circuit. However...

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Problems solved by technology

However, due to the large leakage current of the PMOS formed by the low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) material, the data update period is longer when driving at a low frame rate. When there is a leakage current in the shift register circuit, the shift register circuit The bit register circuit cannot output a stable control signal, causing the display screen of the display device to flicker, affecting the display effect

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