Real-time processing-oriented multi-core processor storage device and data processing method

Abstract

The invention relates to a real-time processing-oriented multi-core processor storage device and a data processing method. The storage device comprises at least one pipeline memory, N first processingunits and a system bus, wherein the N first processing units are connected with the system bus; a first processing unit which comprises a first processor core and a CACHE connected with the first processor core. The first processing unit is connected with the system bus through the CACHE; the first processor core is connected with a port of the at least one pipeline memory; each pipeline memory is a dual-port memory; and two ports of each pipeline memory are connected with data ports of two first processor cores. The data processing method comprises the following steps: when the first processor cores need to transmit data to a target processor core, writing the data into each pipeline memory between the first processor core and the target processor core, and reading the data from pipelinememories between the first processor core and the target processor core by the target processor.

Description

technical field [0001] The invention relates to the technical field of embedded processors, in particular to a storage device and a data processing method for real-time processing-oriented multi-core processors. Background technique [0002] Using a multi-core processor to improve the performance of the processor is a commonly used technology at present. The overall computing capability of the processor chip can be improved by integrating multiple identical processor cores in one chip; it is also possible to form a high-performance processor by integrating multiple heterogeneous processor cores of different structures; Integrate multiple general-purpose processor cores, graphics processor cores, and dedicated accelerators to form a high-performance computing core for domain applications. Multi-core processors usually use multi-level CACHE to improve memory access speed. A single processor core is connected to a shared cache shared by multiple processor cores through a dedi...

AI Technical Summary

Problems solved by technology

In the three cases, the execution time of the program fragment may have a large difference due to the miss of CACHE and the access conflict of the main memory, which will lead to the uncertainty of the execution time of the program in the real-time processing system, and then affect the real-time performance have serious adverse effects

The uncertainty and unpredictability of the running time of this program will affect the real-time performance of the system and reduce the control accuracy of the system control commands.

There are two main solutions at present. One is to pre-load the real-time program into the CACHE, and the other is to disable the CACHE when executing the real-time program. These methods will reduce the system efficiency in a multi-core processor environment and cannot solve the problem of memory access conflicts.

[0008] (2) Data access time is uncertain

When a processor core executes a command output that requires precise timing, if there is system bus competition and IO resource module competition with other processor cores, it will affect the output time of the command, affect the time certainty of command execution, and reduce the control of the command. precision

At the same time, the uncertainty of data access delay will also affect the time certainty of program execution

[0009] (3) Data exchange efficiency between multiple processor cores is low

On the one hand, the main memory is mostly off-chip, and the access delay is relatively large; on the other hand, multiple processor cores accessing the system bus at the same time will cause conflicts and cause additional access delays

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