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Semiconductor packaging method and semiconductor packaging structure

A packaging method and packaging structure technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of edge pins and solder falling off, cracking, etc., to improve the bonding force and strength. , the effect of improving reliability

Active Publication Date: 2020-11-03
SIPLP MICROELECTRONICS CHONGQING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In addition, in packaged products, due to stress concentration on the edge pins derived from copper wiring, the edge pins and solder contact parts may fall off during the drop test and temperature cycle reliability test, and even lead to cracking in severe cases

Method used

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  • Semiconductor packaging method and semiconductor packaging structure
  • Semiconductor packaging method and semiconductor packaging structure
  • Semiconductor packaging method and semiconductor packaging structure

Examples

Experimental program
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Effect test

Embodiment 1

[0042] Such as figure 1 , Figure 2(a)-Figure 2(m) as well as image 3 As shown, the present application provides a semiconductor packaging method and a semiconductor packaging structure.

[0043] figure 1 It is a flowchart of a semiconductor packaging method proposed according to an exemplary embodiment of the present application. Such as figure 1 As shown, the semiconductor packaging method includes the following steps:

[0044] Step 100: Mount the chip to be packaged on a carrier board, with the back side of the chip to be packaged facing up and the front side facing the carrier board;

[0045]Step 200: Covering the chip to be packaged and the exposed carrier with an encapsulation layer to form the encapsulation structure, the encapsulation structure includes opposite first surfaces and second surfaces, the The front side of the chip to be packaged corresponds to the first surface of the encapsulation structure;

[0046] Step 300: Peel off the carrier board to expose...

Embodiment 2

[0114] The content of the semiconductor packaging method in this embodiment is basically the same as that of the semiconductor packaging method in Embodiment 1, the difference is that in step 400, the depth of the opening is equal to the thickness of the encapsulation structure, That is, the opening penetrates the encapsulation structure along the thickness direction, so it is difficult to fill the entire opening through a single electroplating process, but after step 400 and before step 500, the semiconductor packaging method further includes:

[0115] Step 450: forming a metal layer on the inner surface of the opening, which may firstly fill a part of the space in the opening 15 .

[0116] In step 400, as shown in FIG. 4(a), the depth d1 of the opening 15 formed on the second surface 10b of the encapsulating structural member 10 is equal to the thickness t1 of the encapsulating structural member 10, that is, the opening 15 along the thickness The direction T runs through the...

Embodiment 3

[0126] The content of the semiconductor packaging method in this embodiment is basically the same as the semiconductor packaging method in Embodiment 2, the difference is that after step 600, that is, after the formation of the dielectric layer, it also includes: A heat dissipation fin is formed on the second surface of the encapsulation structure, and the heat dissipation fin is connected to the metal protection element exposed on the second surface of the encapsulation structure. Since the depth of the opening is equal to the thickness of the encapsulating structure, that is, the opening penetrates the enclosing structure along the thickness direction, the metal protection formed therein will be exposed on the second side of the enclosing structure. surface.

[0127] Specifically, as shown in FIG. 6(a), a heat dissipation fin 60 is formed on the second surface 10b of the encapsulation structure 10, and the heat dissipation fin 60 and the metal protection member 50 are expose...

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Abstract

The invention provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: providing a packaging structural member for packaging a chip to be packaged; forming an open pore in the first surface of the encapsulation structural member, wherein the open pore is located at the outer side of the to-be-encapsulated chip; forming a redistribution structure on the first surface of the encapsulation structure, and forming a metal protector on the first surface of the encapsulation structure and within the aperture.The semiconductor packaging structure is manufactured through the semiconductor packaging method. According to the invention, the metal protection piece is arranged, so that the stress of the edge canbe effectively absorbed, the rewiring structure beside the metal protection piece is protected, and the reliability of the semiconductor packaging structure is improved; by means of the partial structure of the metal protection part formed in the open hole, the purpose of dispersing stress borne by the rewiring structure located on the edge can be achieved, and meanwhile the binding force betweenthe metal protection part and the plastic package material can be improved.

Description

technical field [0001] The present application relates to the technical field of semiconductors, in particular to a semiconductor packaging method and a semiconductor packaging structure. Background technique [0002] At present, for packaged products, when heating or cooling, pins at different positions are subject to different stresses due to different thermal expansion coefficients, and the stress on the outermost pins (edge ​​pins) of the package body is most affected. [0003] In addition, in packaged products, due to stress concentration on the edge pins derived from copper wiring, the edge pins and solder contact parts may fall off during the drop test and temperature cycle reliability test, and even lead to cracking in severe cases. [0004] Therefore, how to disperse the stress on the edge pins is a problem to be solved in this field. Contents of the invention [0005] One aspect of the present application provides a semiconductor packaging method, which includes...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L23/16H01L23/31H01L23/49H01L23/498
CPCH01L21/56H01L23/16H01L23/3121H01L23/49H01L23/49838H01L2224/18
Inventor 霍炎涂旭峰
Owner SIPLP MICROELECTRONICS CHONGQING CO LTD
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