Three-dimensional memory structure and preparation method thereof

Abstract

The invention provides a three-dimensional memory structure and a preparation method thereof. The preparation method of a three-dimensional memory structure comprises: dividing the step region into afirst connecting region along a second direction, a second connection area and a third connection area, forming an etching buffer layer on the surface of a sacrificial layer of a stacked structure, which is exposed from the top surface of a step formed in a second connection region; forming a contact hole in the step region on which the etching buffer layer is formed, and when the sacrificial layer of the stacked structure is replaced by the gate conductive material, reserving the sacrificial layer in the middle of the second connection region, and ensuring the gate conductive material to be electrically connected with the etching buffer layer in the edge region of the second connection region, so that the connection column in the contact hole can be electrically connected with the gate layer through the etching buffer layer. By utilizing the method, the process difficulty of etching the contact hole in the step region can be reduced, and the risk of bridging word lines of different layers during etching of the contact hole is eliminated.

Description

technical field [0001] The invention belongs to the field of semiconductor design and manufacture, and in particular relates to a three-dimensional memory structure and a preparation method thereof. Background technique [0002] In general, a three-dimensional memory includes a gate stack structure formed by alternately stacking gate layers and interlayer dielectric layers, and a contact column (Contact, CT for short) is electrically connected to the gate in a step region of the gate stack structure. However, in the actual manufacturing process of the three-dimensional memory, in order to achieve a good electrical connection between the connecting column and the gate layer in the stack structure, it is first necessary to etch a contact hole in the dielectric layer covering the gate stack structure until the contact hole Exposing the surface of the gate layer in the step region, and then filling the contact hole with a metal material for forming a connecting column. [0003]...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional memory structure and its preparation method, which is used to solve the problem that the gate layer is easily hit when the contact hole is formed by etching in the existing 3D NAND preparation process. When forming a connection column in the contact hole, it will cause a technical problem of shorting between different gate layers

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