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Thin film transistor substrate and preparation method of thin film transistor substrate

A technology for thin film transistors and substrates, which is applied in the manufacture of transistors, semiconductor/solid-state devices, electric solid-state devices, etc., can solve the problems of complex preparation process, many mask manufacturing processes, and high manufacturing cost of thin film transistors, and achieves reduction of mask mask plate processes. , the effect of reducing production costs and simplifying the structure

Active Publication Date: 2020-09-25
SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing top-gate thin-film transistor manufacturing technology, the problems of many photomask manufacturing processes in the manufacturing process, complex manufacturing process, and high manufacturing cost of thin-film transistors have been solved.

Method used

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  • Thin film transistor substrate and preparation method of thin film transistor substrate
  • Thin film transistor substrate and preparation method of thin film transistor substrate
  • Thin film transistor substrate and preparation method of thin film transistor substrate

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Embodiment Construction

[0037] The technical solutions in the embodiments of the disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the disclosure. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

[0038] Currently, there is no overlap between the source / drain electrodes and the gate in top-gate self-aligned structure metal oxide thin film transistors, so it has lower parasitic capacitance and better extension performance, as well as lower signal delay However, when preparing top-gate thin film transistors, more photomask and mask steps are required, which is not conducive to process simplification and product cost reduction.

[0039] Such as figure 1 as shown, figure 1 A schema...

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Abstract

The invention provides a thin film transistor substrate and a preparation method thereof. The thin film transistor substrate comprises a metal layer, a buffer layer, a switching thin film transistor and a driving thin film transistor. The metal layer comprises a source electrode of the switching thin film transistor, a first metal layer and a shading layer. The source electrode, the first metal layer and the shading layer are formed by patterning the same metal layer and are arranged in the same layer. According to the structure disclosed by the embodiment of the invention, a flat layer structure is omitted, and the structure of the thin film transistor substrate is effectively simplified. Meanwhile, the photomask template process in the preparation process is reduced, the photomask frequency is reduced, the production process is simplified, and the production cost is reduced.

Description

technical field [0001] The present disclosure relates to the technical field of display manufacturing, and in particular to a thin film transistor substrate and a method for preparing the thin film transistor substrate. Background technique [0002] At present, a thin film transistor (TFT) is a main switching element in a liquid crystal display device and an active matrix driven organic electroluminescent display device, and its performance is directly related to the development direction of the display device. [0003] Thin-film transistors have many different structures. Traditional bottom-gate thin-film transistors tend to generate large parasitic capacitance, high signal delay rate and large device size due to the large overlapping area between the gate and source-drain electrodes. The top gate thin film transistor has lower parasitic capacitance, better ductility, and signal delay rate because there is no overlap between the source and drain electrodes and the gate. At ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/786H01L29/417H01L27/12H01L21/77
CPCH01L27/1214H01L27/1288H01L29/41733H01L29/78633
Inventor 卢马才
Owner SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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