Registration method and system for circuit design layout and electron microscope scanning image, circuit design layout and imaging error calculation method thereof

A technique for electron microscope scanning and circuit design, which is applied in computing, image enhancement, image analysis, etc., can solve problems such as circuit design layout and electron microscope scanning image registration difficulties, and achieve accurate error calculation, fast and accurate registration, and accurate registration Effect

Active Publication Date: 2020-08-07
SHENZHEN JINGYUAN INFORMATION TECH CO LTD
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the current problem of difficult registration of circuit design layout and electron microscope scanning image, the present invention proposes a registration method and system for circuit design layout and electron microscope scanning image, circuit design layout and its imaging error calculation method and electronic equipment

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Registration method and system for circuit design layout and electron microscope scanning image, circuit design layout and imaging error calculation method thereof
  • Registration method and system for circuit design layout and electron microscope scanning image, circuit design layout and imaging error calculation method thereof
  • Registration method and system for circuit design layout and electron microscope scanning image, circuit design layout and imaging error calculation method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0035] see figure 1 , The first embodiment of the present invention provides a method 10 for registering a circuit design layout and a scanning electron microscope image, through which the circuit design layout and its corresponding scanning electron microscope image can be registered.

[0036] The registration method 10 of the circuit design layout and the scanning electron microscope image includes:

[0037] Step S1: providing a circuit design layout to be registered and an electron microscope scan image, the circuit design layout to be registered includes at least one design pattern, and the electron microscope scan image to be registered includes at least one scan pattern corresponding to the at least one design pattern ; The design pattern covers its corresponding scanning pattern;

[0038] Step S2: Process the circuit design layout to be registered to obtain the design version Figure II value image, the design version Figure II The grayscale value in the design patte...

Embodiment approach

[0061] see Figure 4B , as another implementation, step Sb1 includes:

[0062] Step Sb1-1': corroding the electron microscope scanning image to be registered; and

[0063] Step Sb1-2': Obtain the outline of the scan pattern through an edge detection algorithm in image processing.

[0064] Since the scan pattern outline in the electron microscope scan image usually has a certain width, which will lead to inaccurate acquisition of the scan image outline, in step Sb1-1', the electron microscope scan image to be registered is etched to refine the scan pattern outline width , to avoid the situation of two edges in edge detection.

[0065] see Figure 4C , as a specific implementation, in step Sb1, adaptive threshold binarization is used to extract the contour, which includes:

[0066] Step Sb1-a: setting the grayscale threshold; and

[0067] Step Sb1-b: comparing the pixel values ​​of the pixels of the electron microscope scanning image to be registered with the gray threshold...

no. 2 example

[0075] see Figure 6 , the second embodiment of the present invention provides a registration system 20 of a circuit design layout and an electron microscope scanning image. The registration system 20 of a circuit design layout and an electron microscope scanning image includes an input module 21, a binary image processing module 22, and a Gaussian filter module 23 and registration module 24.

[0076]The input module 21 is used to input and provide the circuit design layout to be registered and the scanning electron microscope image, the circuit design layout to be registered includes at least one design pattern, and the scanning electron microscope image to be registered includes at least one pattern corresponding to the at least one design pattern. A scan pattern; the design pattern covers its corresponding scan pattern.

[0077] The binary image processing module 22 is used to process the circuit design layout to be registered to obtain the design version Figure II value ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a registration method for a circuit design layout and an electron microscope scanning image. The registration method comprises the following steps: S1, providing the circuit design layout and the electron microscope scanning image to be registered; S2, processing the circuit design layout to be registered to obtain a binary image of the design layout; processing the electronmicroscope scanning image to be registered to obtain an electron microscope scanning binary image; S3, performingGaussian filtering on the design layout binary image and the electron microscope scanning binary image so that the gray value of the central axis of the area corresponding to the design pattern and the scanning pattern is enabled to be maximum; and S4, performing registration accordingto the central axes of the design pattern and the scanning pattern. The invention further provides a registration system of the circuit design layout and the electron microscope scanning image, the circuit design layout, an imaging error calculation method of the circuit design layout and electronic equipment. The circuit design layout, the electron microscope scanning image registration method and system, the circuit design layout, the imaging error calculation method of the circuit design layout and the electronic equipment have the advantages of accurate registration, accurate error calculation and the like.

Description

【Technical field】 [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a registration method and system for a circuit design layout and an electron microscope scanning image, a circuit design layout and its imaging error calculation method, and electronic equipment. 【Background technique】 [0002] As the size of the pattern features on the mask continues to decrease, the diffraction phenomenon of light becomes more and more significant, which causes the imaging on the silicon wafer to be deformed and indistinguishable. This phenomenon is called the Optical Proximity Effect (Optical Proximity Effect) . In order to improve the imaging quality, people can optimize the pattern on the mask to correct the optical proximity effect, namely OPC (Optical Proximity Correction). Therefore, OPC plays a very important role in the photolithography process of semiconductor device manufacturing. [0003] However, as the circuit design layout of li...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/392G06T5/00G06T5/30G06T7/30
CPCG06T5/30G06T5/002G06T7/30G06T2207/30148G06F30/392G06T7/13G06T7/337G06T2207/10061G06T11/40
Inventor 闫歌李强
Owner SHENZHEN JINGYUAN INFORMATION TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap