Packaging structure of power MOSFET chip

Abstract

The invention discloses a packaging structure for a power MOSFET chip. The structure comprises the MOSFET chip which comprises a grid electrode and a source electrode on the front surface and a drainelectrode on the back surface, a first electric conductor which is electrically connected with the drain electrode on the back surface of the MOSFET chip, and a second electric conductor which is electrically connected with the source electrode on the front surface of the MOSFET chip through crimping packaging. A stress buffer area is arranged in the area, occupying the front surface of the MOSFETchip, of the source electrode, and the edge, making contact with the source electrode, of the second electric conductor is located in the stress buffer area. The part, corresponding to the stress buffer area, of the MOSFET chip does not contain a cellular structure. By additionally arranging the stress buffer area on the source electrode of the MOSFET chip, the damage of the edge stress concentration of the second electric conductor to the cellular structure in the MOSFET chip can be remarkably reduced, and the compression resistance and the reliability of the MOSFET chip are greatly improved. Meanwhile, the double-sided heat dissipation capacity is reserved, which improves the power level of a device.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure of a power MOSFET chip. Background technique [0002] At present, high-power MOSFET devices can be divided into soldering type and crimping type according to the packaging process. The common welding type power MOSFET packaging structure mainly includes busbar electrodes, bonding wires, chips, soldering layers, lining boards and substrates. key link. In order to improve the reliability of the device, it is required that the coefficients of thermal expansion of each part of the material match, the heat dissipation characteristics are good, and the connection interface is as few as possible and the connection is firm. As the power level continues to increase, under the constraints of welding, wire bonding and other process conditions, the failure problems such as chip soldering layer degradation and lead shedding in the soldered structure are...

AI Technical Summary

Problems solved by technology

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the fact that in the prior art, the crimp packaged chip cannot ensure the uniform distribution of pressure on the contact surface between the conductor and the chip, and the cell structure of the chip near the edge of the conductor is prone to occur due to the large stress. Fracture failure defects, thus providing a packaging structure for power MOSFET chips

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