Three-dimensional stacked gate-all-around transistor and its preparation method

Abstract

The present invention provides a three-dimensional stacked gate-all-around transistor and a preparation method thereof. The method includes: 1) providing an SOI substrate with grooves formed in its insulating layer; Semiconductor nanowire structure; 3) Rounding and thinning the semiconductor nanowire structure; 4) Forming a fully enclosed gate dielectric layer and gate electrode layer on the surface of the semiconductor nanowire; 5) Using the gate electrode layer as a mask, ions Implanting to form a source region and a drain region; 6) removing the gate dielectric layer outside the gate electrode layer; 7) forming a source electrode and a drain electrode in the source region and the drain region. The invention adopts the gate electrode layer as a mask to carry out the self-alignment implantation of the source region and the drain region, which can effectively improve the process stability and implantation precision. The invention does not need isotropic wet etching when preparing semiconductor nanowires, and can effectively avoid the generation of concave cavities. The invention can effectively improve the integration degree of devices.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit design and manufacture, in particular to a three-dimensional stacked gate-all-around transistor and a preparation method thereof. Background technique [0002] As microelectronic devices continue to shrink, it is expected that the existing FinFET technology will face a large technical bottleneck at the 5nm and 3nm nodes, and the device performance will no longer be greatly improved as the device size continues to decrease. This requires us to adopt new device technologies, such as the use of new device materials (such as strained silicon, silicon germanium, germanium, III-V semiconductors, etc.), and the use of new device structures (such as nanowire gate-all-around transistors, etc.). [0003] The nanowire gate-all-around transistor can confine the conductive channel to the center of the nanowire instead of the interface between the nanowire and the gate oxide layer, which greatly ...

AI Technical Summary

Problems solved by technology

[0015] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional stacked gate-all-round transistor and its preparation method, which are used to solve the problems of low process stability and low integration in the preparation of gate-all-round transistors in the prior art. low problem

Images