Three-dimensional NAND flash memory device and preparation method thereof

Abstract

The invention provides a three-dimensional NAND flash memory device and a preparation method thereof. The preparation method comprises the steps of providing a semiconductor substrate extending alongthe horizontal direction, and forming a plurality of peripheral devices on the semiconductor substrate; forming a bottom connection layer on the plurality of peripheral devices; forming at least two planar NAND junctionless flash memory strings on the bottom connecting layer; and forming a back-end interconnection layer on the at least two planar NAND junctionless flash memory strings; combining aplanar NAND junctionless flash memory string structure with a peripheral device to construct the three-dimensional NAND flash memory device. According to the present invention, the quick reading characteristic of the planar NAND junctionless flash memory strings is well utilized, the planar NAND junctionless flash memory strings can be well compatible with a logic unit, a standard independent NAND flash memory product can be manufactured, but also an embedded NAND flash memory product can be manufactured according to the use condition under the condition that the product performance is guaranteed; and on the other hand, by adopting the mode, the horizontal occupied area of the two-dimensional NAND flash memory device can be effectively reduced, and the space use efficiency of the device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor storage devices, in particular to a three-dimensional NAND flash memory device and a preparation method thereof. Background technique [0002] With the continued emphasis on highly integrated electronics, there is a continuing need for semiconductor memory devices that operate at higher speeds and lower power and have increased device densities. In order to improve the density of memory, the industry has made extensive efforts to develop methods for reducing the size of two-dimensionally arranged memory cells. As the size of memory cells of two-dimensional (2D) memory devices continues to decrease, its manufacturing process encounters various challenges: physical limits, such as exposure technology limits, development technology limits, and storage electron density limits, etc., resulting in conflicts and interferences in storage signals significantly increased, making it difficult to perform multi-l...

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Problems solved by technology

[0004] In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of three-dimensional NAND flash memory device and preparation method thereof, be used to solve the 3D NAND flash memory device of the multi-layer NAND storage string with vertical alignment channel in the prior art Difficulty in forming embedded chips etc.

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