Zero-value register implementation method and device

Abstract

The invention relates to an out-of-order superscalar microprocessor design technology, in particular to a zero-value register implementation method and device. The method comprises the following stepsof: adding an identification field is_zero in a register renaming mapping table, wherein the identification field is_zero represents whether the register is a zero value register or not; and readingand transmitting the field in the register renaming stage to an execution component step by step along with an assembly line, wherein the identification field is_zero is used as a selection signal, data 0 is directly selected when a source operand comes from a zero value register, and data does not need to be obtained from a bypass or a physical register. According to the method, the complexity ofregister renaming, physical register writing and data bypass logic is reduced, and the zero-value register implementation method and device are suitable for the advantage of simple logic implementation.

Description

technical field [0001] The invention relates to out-of-order superscalar microprocessor design technology in the technical field of microprocessor design, in particular to a method and device for realizing a zero value register. Background technique [0002] Processor architectures usually define a zero-valued register, writes to this register are ignored, and reads of this register always return the constant value 0. The zero-value register and the general-purpose register are compiled uniformly. Some architectures use the 0th general-purpose register as the zero-value register, such as RISC-V, and some architectures use the largest number of general-purpose registers as the zero-value register, such as ARM. [0003] When designing a microprocessor, general-purpose registers including zero-value registers are usually organized into a data array, and the data array is indexed by the register number to realize reading and writing of the registers. For the data unit correspon...

AI Technical Summary

Problems solved by technology

When register renaming, if it is not distinguished whether it is a zero-value register or an ordinary general-purpose register, then the zero-value register will be renamed, and will be mapped to different data units at different stages of program execution. Each data unit is It is necessary to judge whether it is necessary to read zero-write ignore, and the logic is complicated; if the zero-value register is not renamed so that it is always mapped to a fixed data unit, then only the specified data unit is required to read zero-write ignore, but In the register renaming stage, it is necessary to determine whether the register operand is a zero-value register, which increases the logic complexity of register renaming

In addition, out-of-order superscalar microprocessors will implement data bypass in order to improve performance. For zero-valued registers, data 0 should be bypassed instead of original data when data is bypassed. This requires data bypass logic to determine whether it is a zero-valued register. bypass, which increases the complexity of the implementation

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