Chip packaging structure and manufacturing method thereof

Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure includes: a first rewiring layer; a first chip electrically connected to the first rewiring layer; a first plastic package encapsulating the first chip; a second chip arranged on the first chip away from the first rewiring layer. One side of the wiring layer is electrically connected to the first rewiring layer; the second plastic package encloses the second chip, and the thermal expansion coefficient of the second plastic package is different from that of the first plastic package. The first chip is encapsulated by the first plastic package, and the second chip is packaged by the second plastic package, so that the thermal expansion coefficients of the first plastic package and the second plastic package are different, and the first plastic package and the second plastic package expand during the formation process. Different from the thermal stress caused by shrinkage, it achieves the purpose of balancing the overall stress of the plastic package, thereby reducing the overall warpage of the packaging structure, effectively controlling the warpage during the packaging process, improving the reliability of the package, and facilitating the subsequent semiconductor device manufacturing process. , to ensure the quality of semiconductor devices and improve product yield.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology, three-dimensional stacked semiconductor devices have been widely used as a process that can effectively reduce the physical size of semiconductor devices. In a three-dimensional package-on-package semiconductor device, active circuits such as logic, memory, processor circuits, etc. are fabricated on separate wafers and packages. Two or more packages are mounted one on top of the other, ie stacked, to allow a higher level of integration of the packages. In addition, stack-package semiconductor devices can achieve smaller form factors, higher cost-effectiveness, enhanced performance, and lower power consumption. [0003] In the prior art, the overall plastic packaging or step-by-step plastic packaging is usually ...

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Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defects in the prior art that the packaging structure warps during the multi-chip packaging process and affect the subsequent manufacturing process and the quality of semiconductor devices, thereby providing a new chip packaging structure and its manufacturing method

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