Integrated circuit packaging body and preparation method thereof

Abstract

The invention provides an integrated circuit packaging body and a preparation method thereof. The packaging body comprises a chip which comprises a functional surface and a non-functional surface which are oppositely arranged, and the functional surface is provided with a plurality of first bonding pads which are arranged at intervals. The packaging body further comprises a substrate, wherein thesubstrate and the chip are oppositely arranged at intervals. A second bonding pad is arranged at the position, corresponding to the first bonding pad, of the substrate. The packaging body further comprises a number of first welding bodies. Each first welding body comprises a conductive supporting piece and a first welding flux layer at least located at the end of one side of the conductive supporting piece, and the first welding bodies are electrically connected between part of the first bonding pads and the corresponding second bonding pads. The packaging body further comprises a number of second welding bodies which comprise second welding flux layers, and the second welding bodies are electrically connected between the remaining first bonding pads and the corresponding second bonding pads. The melting point of the conductive supporting pieces is greater than the melting points of the first welding flux layer and the second welding flux layer. According to the invention, the probability that the chip inclines relative to the substrate during backflow can be reduced.

Description

technical field [0001] The present application relates to the field of packaging technology, in particular to an integrated circuit package and a preparation method thereof. Background technique [0002] Among integrated circuit packages, ball array packaging is a relatively common product packaging method. The packaging method specifically includes: using a ball planting machine to form solder balls on the first pad of the chip, and then using surface mount technology to mount and reflow solder the chip and the substrate. [0003] The inventors of the present application have found in the long-term research process that during the reflow soldering process of the above-mentioned integrated circuit package, due to the warpage of the substrate or the tilt of the chip during mounting, the solder balls on the chip may not match the solder balls at the corresponding positions. The second pad on the substrate is connected, thereby causing an open circuit of the solder joint, so t...

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Problems solved by technology

[0003] The inventors of the present application have found in the long-term research process that during the reflow soldering process of the above-mentioned integrated circuit package, due to the warpage of the substrate or the tilt of the chip during mounting, the solder balls on the chip may not match the solder balls at the corresponding positions. The second pad on the substrate is connected, which leads to an open circuit of the solder joint, which makes the IC package fail

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