FPGA wiring method and device

Abstract

The invention provides an FPGA wiring method and a device. The method comprises the steps of through determining starting node serving as a wiring starting point, dividing each end point node corresponding to the starting node into at least one end point set, taking one end point set as a logic end point; establishing a wiring path from the starting node to each end point set; according to the wiring mode, it is avoided that a wiring path needs to be established for each terminal point, wiring is completed in the node traversal process as few as possible, the use efficiency of wiring resourcesis improved, and therefore wiring conflicts are reduced, the wiring speed is increased, and the memory overhead is reduced.

Description

technical field [0001] The invention relates to the technical field of field programmable gate array (FPGA), in particular to an FPGA wiring method and device. Background technique [0002] With the rapid development of electronic technology, the pace of digital circuit design is gradually accelerating. The advent of FPGA makes the design of digital circuits simple and fast. With the diversification of application scenarios and market demands, the design scale of digital circuits continues to expand, the logic processing capability of FPGA design software is challenged, and the control of running time and memory overhead has become an important topic. [0003] At present, the more common wiring algorithm is the A* algorithm, which is a graph search algorithm driven by a cost value function. The basic formula of the A* algorithm is: [0004] f(n)=g(n)+h(n) [0005] Among them, n is an intermediate node, g(n) is the actual cost value from the start node to node n, and h(n) ...

AI Technical Summary

Problems solved by technology

[0008] The invention provides an FPGA wiring method and device, which solves the problems of long wiring running time and large memory consumption in the existing large-scale circuit design

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