Method for Biasing Outputs of a Folded Cascode Stage in a Comparator and Corresponding Comparator

A folded cascode, comparator technology, applied in amplifiers with semiconductor devices/discharge tubes, multiple input and output pulse circuits, amplifiers, etc. Output speed, effect of increasing travel time

Pending Publication Date: 2020-01-14
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] In comparators where high efficiency is desired, especially in terms of input-output propagation speed, these stray capacitances are extremely detrimental and difficult to reduce in the art

Method used

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  • Method for Biasing Outputs of a Folded Cascode Stage in a Comparator and Corresponding Comparator
  • Method for Biasing Outputs of a Folded Cascode Stage in a Comparator and Corresponding Comparator
  • Method for Biasing Outputs of a Folded Cascode Stage in a Comparator and Corresponding Comparator

Examples

Experimental program
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Embodiment Construction

[0036] figure 2 An exemplary integrated circuit CI is shown, which includes a comparator CMP configured to generate a voltage at a first voltage level (logic '1') when the level of the positive input voltage IN+ exceeds the level of the negative input voltage IN-. ) signal VCOMP.

[0037] The comparator CMP comprises a differential preamplification stage PAD receiving positive and negative input voltages on respective inputs IN+, IN- (referred to as positive and negative inputs, respectively).

[0038] image 3 An example of a differential preamplification stage PAD and a power supply device configured to provide a bias current Ib to the stage PAD is shown.

[0039] The differential preamplifier stage PAD includes two pairs of differential transistors. One differential pair, called a p-type conduction differential pair, includes two PMOS transistors MP+, MP- whose sources are coupled to a p-type conduction bias node IBP. Another differential pair, called an n-type conduct...

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PUM

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Abstract

The present invention relates to a method for biasing outputs of a folded cascode stage in a comparator and a corresponding comparator. The comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the tworesistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from French patent application No. 1856189 filed on July 5, 2018, the content of which is incorporated herein by reference. technical field [0003] The present invention relates generally to electronic systems and methods, and in particular embodiments, to a method of biasing the output of a folded cascode stage in a comparator and a corresponding comparator. Background technique [0004] In a comparator circuit, two input voltages are compared and an output voltage representing the difference between the input voltages is generated. Comparisons are typically performed by differential transistor pairs. [0005] figure 1 Shown are examples of differential transistor pairs configured to be incorporated into comparators, but with drawbacks in terms of efficiency. [0006] Differential transistor pairs preferably have very close characteristics, especially voltage thresholds, to ensur...

Claims

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Application Information

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IPC IPC(8): H03K5/24
CPCH03K5/2463H03K5/2481H03F3/45134H03F3/45192H03F3/45506H03F2200/78H03F2203/45H03K3/3565
Inventor Y·若利V·比内
Owner STMICROELECTRONICS SRL
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