Retention time violation repair method, device and equipment

Abstract

The invention provides a retention time violation repairing method, device and equipment. The method includes: before layout time sequence optimization, calculating a retention time violation value ofa scanning time sequence path in an integrated circuit in advance according to a netlist of the integrated circuit; determining a buffer combination required for repairing the retention time violation of the scanning time sequence path according to the retention time violation value of the scanning time sequence path; generating a layout constraint according to the layout space corresponding to the buffer combination, and performing layout time sequence optimization according to the layout constraint to reserve the layout space corresponding to the buffer combination for the scanning time sequence path; during a hold time repair phase, inserting the buffer corresponding to the buffer combination into the layout space corresponding to the reserved buffer combination, and the newly insertedbuffer is located in the reserved layout space, so that the placement of the original unit is not influenced, too many wiring resources are not increased, the influence on the design is minimum, andthe iterative period of the design can be remarkably shortened.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a method, device and equipment for repairing hold time violations. Background technique [0002] Hold time repair is an important link in integrated circuit design, and this process directly affects the speed, power consumption, and area of ​​the final circuit. The hold time of the scan chain timing path is the main component of the overall circuit hold time violation. Inserting buffers to increase path delay is a common way to fix hold time. [0003] The traditional design process of integrated circuits includes: netlist generation and layout and layout timing optimization, clock tree construction, hold time repair, routing and post-routing timing optimization, layout output and other stages. Among them, the layout phase determines the physical position and orientation of all standard cells and macro cells (Macro), and the layout and layout timing optimization perf...

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a hold time violation repair method, device and equipment to solve the problem that there is not enough space to insert a buffer in the hold time repair stage, or the newly inserted buffer can only be placed far away from the target area, resulting in scanning The path will occupy more routing resources. On the one hand, the setup time violation of the functional path will be increased. On the other hand, the winding or long trace is more susceptible to coupling noise, which will lead to the deterioration of the scan chain hold time violation.

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