All-digital phase-locked loop frequency synthesizer

Abstract

The invention discloses an all-digital phase-locked loop frequency synthesizer which comprises a numerical control oscillator, a prescaler, a counter, a time-to-digital converter, a first D trigger, asecond D trigger, a differentiator, a first adder, a second adder and a digital filter. The numerical control oscillator is connected with the prescaler, and the prescaler is respectively connected to the counter, the time-to-digital converter and the first D trigger. The first D trigger and the time-to-digital converter are connected to a reference frequency, and the first D trigger is connectedto the second D trigger and the differentiator. The counter is connected to the second D trigger, the second D trigger and the time-to-digital converter are connected to the first adder, and the first adder is connected to the differentiator. The second adder is connected to the frequency control word, the differentiator and the digital filter. The digital filter is connected to the numerical control oscillator. According to the all-digital phase-locked loop frequency synthesizer, the signal time sequence stability is improved, the noise sensitivity is reduced, the quantization noise is reduced, and the method is suitable for a 60GHz communication system.

Description

technical field [0001] The invention belongs to the technical field of frequency synthesizers, in particular to an all-digital phase-locked loop frequency synthesizer. Background technique [0002] The all-digital phase-locked loop (ADPLL) has the advantages of easy integration and high system reliability, but it also has the disadvantages of low operating frequency, complex structure, and difficult noise analysis, so it is not suitable for high-frequency clock generators. In view of this, the 60 GHz communication system in the prior art often uses an analog phase-locked loop. The traditional PLL design is mature and simple, but the signal is transmitted in analog voltage mode, which is easily interfered by other modules when integrated in the system, and requires a high working power supply voltage and high noise characteristics of the power supply. The loop configuration is difficult, and the filter adjustment ability is very limited, resulting in the loop performance not...

AI Technical Summary

Problems solved by technology

The traditional PLL design is mature and simple, but the signals are transmitted in analog voltage mode, which is easily interfered by other modules when integrated in the system, and requires a high working power supply voltage and high requirements on the noise characteristics of the power supply

The loop configuration is difficult, and the filter adjustment ability is very limited, resulting in the loop performance not as good as the full digital phase-locked loop; in addition, the full digital phase-locked loop in the prior art should be applied to the 60GHz communication system, and there will be problems such as insufficient signal timing Problems such as stability and noise are difficult to optimize

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