Three-dimensional memory and method of forming three-dimensional memory

Abstract

The invention provides a method for forming a three-dimensional storage. The method comprises the steps of: providing a semiconductor structure, wherein the semiconductor structure is provided with asubstrate, the substrate comprises a storage array region and a non-storage array region, the storage array region is provided with a stacked structure and channel holes passing through the stacked structure, and vertical channel structures are formed in the channel holes; forming insulation holes passing through the stacked structure, and forming insulation parts in the insulation holes; and forming through-silicon vias passing through the non-storage array region to reach the substrate, doping the substrate at the bottoms of the through-silicon vias to form an array common source, and filling the through-silicon vias with a conductive material.

Description

technical field [0001] The invention relates to the field of three-dimensional memory, in particular to a three-dimensional memory and a method for forming the three-dimensional memory. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, memory devices with a three-dimensional (3D) structure have been developed and mass-produced in the industry, which improves integration density by three-dimensionally arranging memory cells on a substrate. [0003] In a three-dimensional memory device such as 3D NAND flash memory, the memory array may include a core (core) region with a vertical channel structure and a stepped region with a ladder structure, and multiple memory arrays are connected by gate line gaps (Gate Line Slit, GLS ), the grid line gap extends along the Y-axis direction. [0004] Since the gate line gap extends along the Y-axis direction, it occupies a larger space on the wafer surface, which means that the space avail...

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Problems solved by technology

[0004] Since the gate line gap extends along the Y-axis direction, it occupies a larger space on the wafer surface, which means that the space that can be used to form a storage array becomes smaller, which will reduce the charge storage density of the storage space.

And the grid line gap extends along the Y-axis direction, so that the wafer is unbalanced in the X-axis direction (perpendicular to the grid line gap direction) and the Y-axis direction, causing the wafer to warp

In addition, since the gate line gap occupies a larger space on the wafer surface, the area of ​​the source wire formed in the gate line gap will increase accordingly, which increases the risk of short circuit leakage between the gate and source wires in the memory array.

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