Bonding structures and methods of forming them

Abstract

The present invention relates to a bonding structure and a method for forming the same, comprising: providing two substrates, each of which includes a dielectric layer and a metal interconnection formed in the dielectric layer with an exposed top surface; The surface of the metal interconnection at the bonding position forms a barrier layer, and when the two substrates are provided with a metal interconnection at the opposing bonding position, at least a barrier layer is formed on the top surface of the larger-sized metal interconnection. , the barrier layer is a conductive material and can block the diffusion of metal atoms; the surfaces of the two substrates are bonded oppositely, and the barrier layer is located between the metal interconnections of the two substrates. The barrier layer can prevent the metal atoms in the metal interconnection from diffusing to the adjacent dielectric layer, avoid the electrical performance and reliability deterioration of the device caused by the metal atom diffusion, and improve the reliability of the bonded device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a bonding structure and a forming method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] The 3D NAND flash memory structure includes a memory array structure and a CMOS circuit structure above the memory array structure. The memory array junction and the CMOS circuit structure are usually formed on two different wafers, and then bonded to The CMOS circuit wafer and the ...

AI Technical Summary

Problems solved by technology

[0004] However, in the prior art, at the bonding surface of the metal interconnection between the memory array structure and the CMOS circuit structure, metal atoms are prone to diffusion and electromigration during the heating and cooling process of the bonding process and after bonding, so that the metal bond Pores are generated in the joint surface, resulting in leakage, shortened electromigration life, etc., which reduces the reliability of the product

In the prior art, in order to reduce the above problems, many adjustments and reliability control of the chemical mechanical polishing process for forming metal interconnections are required, resulting in increased costs

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