Programmable super-speed advanced setting type frequency divider

Abstract

The invention relates to a programmable super-speed advanced setting type frequency divider. The programmable super-speed advanced setting type frequency divider comprises a first NOR gate, a first NAND gate, a second NOR gate, a 0-th bit frequency division module, the first bit frequency division module and N third bit frequency division modules. Through the programmable super-speed advanced setting type frequency divider disclosed by the invention, the circuit structure is simple, a full-digital circuit design is adopted, the reusability is strong, the area overhead is low, and the scale iseasy to extend; 2 to 2N frequency division values can be realized in a programmable way, and the programming range is extensive; the setting is performed by adopting a method of quickly presetting internal latch node states of various frequency-division modules, a register setup problem caused by over-high input clock frequency is avoided, and the super-speed frequency division can be realized.

Description

technical field [0001] The invention relates to a programmable ultra-high-speed super-predigital frequency divider, which belongs to the technical field of integrated circuits. Background technique [0002] The frequency divider is located between the Voltage Controlled Oscillator (VCO) and the Phase Frequency Detector (PFD) in the Phase Locked Loop (PLL), and its function is to reduce the VCO output signal frequency , and feed it back to the PFD for phase and frequency comparison with the reference signal. [0003] Figure 7 Shown is the 8 / 9 dual-mode frequency divider realized by the design method of asynchronous logic circuit. When the frequency-division ratio control MC signal is at low level, the detector circuit stops working to realize 8-frequency division; when the output signals of MC and each frequency divider are at high level, the detector generates a negative pulse, and the negative pulse The pulses "swallow" one cycle of the clock signal, achieving a divide b...

AI Technical Summary

Problems solved by technology

The programmable frequency divider is a frequency divider with a variable frequency division ratio. The advantages of the traditional programmable frequency divider are regular structure, convenient layout and fast speed. However, when the frequency division ratio is large, the signal is transmitted to the last stage The delay of the frequency divider becomes larger, reducing the performance of the frequency divider, and the area overhead is large

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