3D stacked image sensor

Abstract

The invention discloses a 3D stacked image sensor. The 3D stacked image sensor comprises a pixel array, an analog-to-digital conversion unit array and a memory array. The image sensor is composed of an upper layer chip and a lower layer chip stacked up and down. The pixel array includes a plurality of pixel units for converting an optical signal into an analog electrical signal and is located on the upper layer chip. The analog-to-digital conversion unit array includes a plurality of analog-to-digital conversion units for converting the analog electrical signals into digital electrical signalsand is located on the lower layer chip. The memory array includes a memory cell array and a logic circuit array, the memory cell array includes a plurality of memory cells for storing the converteddigital electrical signals, the logic circuit array includes a plurality of logic circuits for controlling reading and writing of the memory cells; and the memory array is located at the lower layer chip. The image sensor frame rate can be improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a 3D stacked CMOS image sensor. Background technique [0002] With the development of CMOS integrated circuit technology, the application of electronic products in daily life is becoming more and more extensive. Provided essential technical support. In practical applications, high frame rate image sensors can provide more accurate and real-time image information, and can play an important role in areas such as intelligent driving, rapid identification, and precise capture. However, in existing products, since the image data is read out and transmitted row by row, the frame rate of the image sensor is determined by the conversion and readout time of each row of data and the number of rows. For the current high-definition large pixel array, due to the constraints of the row time and the total number of rows The frame rate is greatly limited. [0003] High integration and...

AI Technical Summary

Problems solved by technology

However, the current double-layer 3D stacked chip still adopts the method of reading out row by row or multi-row in groups. Due to the slow data transmission speed, after the previous frame of image exposure, it must wait for the data to be completely converted before proceeding to the next frame of image data. Therefore, although the existing double-layer 3D stacked chips have improved integration, the frame rate has not been greatly improved due to the limited chip area.

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