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Gate structure and method thereof

A gate dielectric and metal gate technology, applied in the field of gate structure and its formation, can solve problems such as not proving that the existing process is completely satisfactory

Active Publication Date: 2022-06-24
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Therefore, the existing process has not proven to be completely satisfactory in all respects

Method used

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  • Gate structure and method thereof
  • Gate structure and method thereof
  • Gate structure and method thereof

Examples

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Embodiment Construction

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. For example, in the following description, forming the first part over or on the second part may include embodiments in which the first part and the second part are formed in direct contact, and may also include between the first part and the second part Embodiments in which additional components may be formed between, so that the first and second components may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurat...

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Abstract

Embodiments of the invention relate to methods and structures for providing a high voltage transistor (HVT) including a gate dielectric, wherein at least a portion of the gate dielectric is disposed within a trench disposed within a substrate. In some aspects, gate oxide thickness can be controlled by trench depth. By providing the HVT with the gate dielectric formed within the trench, embodiments of the present invention provide the top gate stack surface of the HVT and the low voltage transistor (LVT) being formed on the same substrate approximately coplanar with each other. The top gate stack surface while providing a thick gate oxide for HVT. Furthermore, because the top gate stack surface of the HVT and the top gate stack surface of the LVT are substantially coplanar with each other, over-polishing the HVT gate stack can be avoided.

Description

technical field [0001] Embodiments of the present invention relate generally to the field of semiconductors, and more particularly, to gate structures and methods of forming the same. Background technique [0002] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices capable of simultaneously supporting more increasingly complex and sophisticated functions. Accordingly, an ongoing trend in the semiconductor industry is to manufacture integrated circuits (ICs) that are low cost, high performance, and low power consumption. To date, these goals have been largely achieved by scaling down the size of semiconductor ICs (eg, minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling down also creates an increased level of complexity in the semiconductor fabrication process. Accordingly, enabling continued advancement of semiconductor ICs and devices requires similar a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/336H01L29/423H01L29/78H10N97/00
CPCH01L29/401H01L29/4236H01L29/42364H01L29/66621H01L29/78H01L21/823814H01L21/823857H01L21/823878H03K19/018521H01L27/0922H01L28/40H01L29/66492H01L21/32055H01L21/3213H01L21/304H01L21/31051H01L29/66484H01L21/823481H01L21/823462
Inventor 郑安皓郭舫廷
Owner TAIWAN SEMICON MFG CO LTD
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