A shared on-line debugging method based on FPGA prototype verification system

Abstract

The invention provides a shared on-line debugging method on a prototype verification system based on FPGA. The debugging method comprises: loading circuit files, selecting signals, mapping signals andports, generating circuit bin files, remotely burning the bin files, setting triggering conditions, and debugging. The device of the invention comprises a server end, an FPGA prototype verification board and a client, the server end comprises a server end program, the client includes a client program, the client program provides a visual debugging interface for a user, including RTL code viewing,variable name mapping, secondary mapping in ECO, etc. The invention discloses a shared on-line debugging method based on FPGA prototype verification system, which can improve the usage rate of FPGA prototype verification, reduce the use cost, and greatly improve the debugging speed of circuit design engineer.

Description

technical field [0001] The invention belongs to the technical field of digital circuit design, in particular to a shared online debugging method based on an FPGA prototype verification system. Background technique [0002] As the semiconductor industry enters the deep sub-micron era, the scale, complexity, and cost of ASIC design are increasing significantly. Especially after entering 90nm, the overall ASIC design cost increases by 20%. Even if the 130nm process is adopted, the single ASIC manufacturing cost is also high More than hundreds of thousands of dollars, if the chip tape-out fails, not only will the NRE cost be lost, but the tape-out again will be delayed for several months or even a year, and the market opportunity will be lost. [0003] Verification accompanies the whole process of ASIC design, from custom design system specification and code implementation, to final netlist and back-end layout and routing, etc., verification work has been going hand in hand, ASI...

AI Technical Summary

Problems solved by technology

[0005] Traditional simulation technology is far from meeting the speed requirements of the current complex ASIC verification. Software simulators and formulated software models are very popular, but they can no longer meet the needs of users. Hardware accelerators have better performance, but they are expensive and expensive. It is inconvenient to use, and for some applications with high-speed data processing, such as MPEG video processing, it still cannot achieve the required performance, and now more expensive and more complex hardware emulators on the market cannot meet the current ASIC design performance requirements

[0006] As the front-end part of the traditional ASIC design or SoC design verification environment, the main method of functional verification is software simulation. One of the problems of various functional verification is the amount of data to be collected and stored. If you want to monitor a large number of Signals can slow down the simulation significantly, and lengthy simulations can lead to larger amounts of data. The main advantage of software simulation is full visibility into the design, and the main disadvantage is slowness, even on powerful, high-end workstations. However, software simulation of today's large SoC designs can only barely achieve a simulation speed of a few Hz (that is, only a few cycles per second of the design's real-time main system frequency), which means that software simulation is often Only for a small part of the design, or tens of frequency cycles for a full-chip design, but tens of thousands or even millions of frequency cycles are required to fully verify a modern SoC design, which requires some kind of Form of hardware-assisted verification, in order to solve the problem of simulation speed, and the cumbersome problems of building and writing test platforms, the present invention proposes a shared online debugging method based on FPGA prototype verification system

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