Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device. The method includes steps: depositing a side wall material layer on the surface of a first patterning layer, and forming a second patterning layer corresponding to a first grid electrode on the side wall material layer; and then etching the side wall material layer by regarding the second patterning layer as a mask, and forming a third patterning layer with a first grid pattern and a second grid pattern. The third patterning layer does not have a severe sparse / dense load effect so that there is no etching difference between the first grid electrode and a second grid electrode formed by etching of a grid layer by employing the third patterning layer a mask, the sparse / dense load effect of the grid electrodes is avoided, the appearance of the second grid electrode with abnormal edges is avoided, and the performance of the manufactured semiconductor device is guaranteed.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for manufacturing a semiconductor device. Background technique [0002] At present, with the rapid development of ultra-large-scale integrated circuits, the integration of chips is getting higher and higher, and the circuit design size is getting smaller and smaller. The various effects caused by the high density and small size of devices have an increasing impact on the semiconductor manufacturing results. It is outstanding that, especially in the process below the 28nm technology node, the change of the critical dimension (CD, Critical Dimension) of the circuit has more and more influence on the performance of the device. As we all know, since the gate usually has the smallest physical size in the semiconductor manufacturing process, and the width of the gate is usually the most important critical dimension on the wafer, the fabrication of the ...

AI Technical Summary

Problems solved by technology

It has been found in practice that when the gates of the dense region and the sparse region are formed in the same etching process, there is an etching difference (I / D loading, or known as sparse / dense loading effect), affected by the I / D loading, the gates at the edge of the dense area tend to have abnormal contours and depths, and the abnormal edge gates will have an abnormality in the middle of the dense area. Both the gate and the gate of the sparse region are adversely affected, which in turn affects the performance of the device

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