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Multi-core cascade-based cycle accurate model of vector calculation hardware accelerator

A hardware accelerator, accurate model technology, applied in digital computer components, architectures with a single central processing unit, instruments, etc., to achieve the effect of fast simulation speed and high simulation accuracy

Inactive Publication Date: 2018-11-13
NANJING UNIV
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Problems solved by technology

With the increasing complexity of SoC systems, system-level design verification has become a huge challenge in SoC design

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  • Multi-core cascade-based cycle accurate model of vector calculation hardware accelerator
  • Multi-core cascade-based cycle accurate model of vector calculation hardware accelerator

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Embodiment Construction

[0026] The present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation cases.

[0027] The cycle-accurate simulation model of the multi-core cascade of the vector operation hardware accelerator provided in this embodiment adopts the SystemC cycle-accurate model, including a control module, a transmission module, an operation module and a storage module. The control module generates configuration parameters, which are used to control the interaction with the outside of the model, the working status of each module inside the model, and switch the mode of data transmission, data division and data address mapping according to the number of calculation points of different algorithms; the transmission module receives all The configuration parameters generated by the above control module are used for data and address transmission with the outside of the dedicated processor core, inside the dedicated processor core, and ...

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Abstract

The invention provides a multi-core cascade-based cycle accurate simulation model of a vector calculation hardware accelerator. The SystemC-based cycle accurate model comprises a control module for generating and outputting configuration parameters, a transmission module for receiving the configuration parameters and finishing data and address transmission outside a special processor core, data and address transmission in the special processor core and data and address transmission among a plurality of special processor cores in a cascade mode according to the configuration parameters, an operation module for receiving the configuration parameters, selecting corresponding basic operation units according to the configuration parameters, building the operation units into an algorithm operation module determined by the configuration parameters and performing operation, and a storage module for receiving the configuration parameters and storing the data required during operation of the operation module and an intermediate result and a final result generated during operation of the operation module according to the configuration parameters. The model has the beneficial effects that multi-core cascade-based system simulation of the vector calculation hardware accelerator is realized; an algorithm with a larger operation scale can be supported; and the simulation speed is high.

Description

technical field [0001] The invention belongs to the field of test simulation and verification platforms, in particular to a multi-core cascaded cycle accurate model of a vector computing hardware accelerator. Background technique [0002] With the rapid development of IC (Integrated Circuit) technology, SoC (System on Chip) has become the development direction of today's integrated circuit design. With the increasing complexity of SoC systems, system-level design verification has become a huge challenge in SoC design. The integrated circuit design circle has been considering how to meet the design requirements of SoC, which requires a system-level design language that can realize the joint description of high-level software and hardware at the same time. [0003] SystemC is a software-hardware co-design language, a system-level modeling language. SystemC is formed by extending the hardware class and simulation core on the basis of C++. Due to the combination of object-orie...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F13/30
CPCG06F13/30G06F15/7846G06F15/7867
Inventor 李丽刘禹楠沈鹏程陈辉丰帆潘红兵何书专
Owner NANJING UNIV
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