A High Frequency and Low Overhead Odd Divider Circuit Based on lfsr

Abstract

The present invention provides a high-frequency and low-overhead odd-number frequency division circuit based on LFSR. Based on the linear feedback shift register, the traditional decimal counting is changed to a pseudo-random counting method, thereby avoiding the increase of the bit width. The complexity of the carry logic climbing problem. Since the LFSR counter is used to replace the traveling wave carry counter in the traditional odd frequency division circuit, the odd frequency division with a higher number of digits is realized. It does not modify the regular structure of the original odd frequency division, and the existing timing constraint rules can be reused. The complexity of the backend implementation is reduced. Compared with the asynchronous design, the traveling wave counter adopts pure synchronous logic, which greatly reduces the design complexity of timing constraints, and is friendly to synthesis tools. Compared with ripple carry counters and Johnson counters, resource overhead can be significantly reduced. It has good scalability, and its advantages are more obvious in the application of higher frequency and higher frequency division coefficient.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an LFSR-based high-frequency and low-overhead odd frequency division circuit. Background technique [0002] Thanks to the rapid development of microelectronics process technology, microelectronic chips represented by processors have entered the frequency era of up to GHz, forming a complex SoC integrating multiple functional components. Among them, in addition to the processor core with high main frequency as the target, it also integrates various frequency-specific functional IPs, such as PCI controllers working at 33 / 66MHz, Flexray controllers working at 80MHz, and working at 12 / 66MHz. 16MHz 1553 controller, etc. Therefore, almost all current SoCs need to design a corresponding clock management unit to divide the high-frequency clock obtained by PLL frequency multiplication to obtain the corresponding low-frequency clock. However, with the rapid increase in the comple...

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Problems solved by technology

[0009] Aiming at the problems existing in the prior art, the present invention provides a high-frequency and low-overhead odd-number frequency division circuit based on LFSR, which is not affected by the counting bit width, does not cause the problem of carry logic complexity, and the simplified design logic can satisfy Timing synthesis under high-frequency clock, while reducing resource overhead, suitable for ASIC design and implementation of frequency division structure

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