Data compressed SoC chip information tracking device and performance optimization method

Abstract

The invention discloses a data compressed SoC chip information tracking device which comprises a selector, an asynchronous FOFO, a tracking controller, a register and a memory. The selector selects atarget tracking bus according to configuration information of the register, the asynchronous FOFO is used for data cache and clock synchronization, the tracking controller is used for condition trigger, information compression and recording, tracking information is configured for the register by a CUP through an AHB, the memory is used for storing tracking result information, and the CUP executesaccess through a slave computer of the AHB.

Description

technical field [0001] The invention belongs to the field of SoC chips, in particular to a data compressed SoC chip information tracking device and a performance optimization method. Background technique [0002] As the SoC architecture becomes more and more complex, due to unreasonable design and planning of the bus architecture, it is likely that the SoC will not achieve the best performance in actual work, so it is necessary to track and record the status information of the bus to analyze the bus Whether the configuration is reasonable. [0003] When most SoCs are running, their internal operating status and performance cannot be observed. On the one hand, this makes it impossible for system application developers to know whether the SoC has reached its peak performance when encountering performance bottlenecks. On the other hand, when system developers encounter problems and need to track certain hardware information, there is no proper way to obtain it. [0004] Most...

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Problems solved by technology

[0002] As the SoC architecture becomes more and more complex, due to unreasonable design and planning of the bus architecture, it is likely that the SoC will not achieve the best performance in actual work, so it is necessary to track and record the status information of the bus to analyze the bus Is the configuration reasonable?

[0003] When most SoCs are running, their internal operating status and performance cannot be observed

On the one hand, this makes it impossible for system application developers to know whether the SoC has reached the optimal performance when encountering a performance bottleneck

On the other hand, when system developers encounter problems and need to track certain hardware information, there is no proper way to obtain

[0004] Most of the current SoCs are based on the bus architecture. In these SoCs based on the bus architecture, the initiation behavior of the bus transmission is complicated when the system is actually running. The default bus access priority and bandwidth arrangement of the hardware design are often not optimal, so as to achieve Less than optimal bus transfer performance and system application performance

[0005] When debugging and optimizing the system architecture, if it is necessary to monitor the state and data of the bus in real time, due to the complexity of the bus signal and the large amount of data, if the normal function serial port is used to send the information to the host computer for monitoring, it will affect the normal operation of the SoC. The working state (that is, intrusive) makes the monitoring results inaccurate; if the on-chip memory is used to store the monitoring information, it will take up a large storage space, thereby increasing the area and power consumption of the SoC

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