Data flow instruction mapping method

A mapping method and data flow technology, applied in the direction of concurrent instruction execution, electrical digital data processing, program control design, etc., can solve problems affecting the execution efficiency of data flow programs, generating a large number of routing packets, and on-chip network congestion, etc., to improve execution Efficiency, reducing the effect of on-chip network congestion

Active Publication Date: 2018-07-17
上海睿伍科技有限公司
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Problems solved by technology

Multi-address shared data routing packets are split during transmission on the on-chip network. If the timing of splitting is not appropriate, a large number of routing packets will be generated in the on-chip network, resulting in congestion in the on-chip network, thereby affecting the execution efficiency of data flow programs.

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specific Embodiment

[0059] The computing unit array in this example constitutes a Mesh grid. The routing algorithm of the on-chip network is X-Y routing, that is, X-axis routing first, and then Y-axis routing. At the same time, the on-chip network transmission routing packet is a multi-address shared data routing packet structure.

[0060] The data flow graph traverses the sub-steps:

[0061] Step 101: The data flow graph traverses the initial state such as figure 1 As shown, the traversal process has two areas, one is the queue area, which is similar to the breadth-first traversal priority queue of the graph, and is used to record the nodes that need to be traversed next, and the other is the buffer area, which is used to record whether the binding instruction is It can be mapped, and a "bundle instruction" refers to "at least two downstream instructions located downstream of the same data flow instruction". In this figure, the initial traversal is node 1 of the data flow graph, so the queue ar...

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Abstract

The invention discloses a data flow instruction mapping method. The method includes the substep of data flow diagram traversing and the substep of instruction mapping. The substep of data flow diagramtraversing is used for traversing each node in a data flow diagram, and the substep of instruction mapping is used for mapping multiple data flow instructions to computing cell arrays of a network onchip respectively. According to the data flow instruction mapping method, an existing data flow instruction mapping method is optimized, PEs (processing elements) corresponding to multiple addressesin a multi-address shared data routing packet during running are located on the same straight line as much as possible according to the topological structure condition of the network on chip and the characteristics of a routing algorithm, the network on chip jam condition caused by splitting of the routing packet is reduced accordingly, and the executing efficiency of data flow programs is improved.

Description

technical field [0001] The invention relates to the field of data flow architecture processor optimization, in particular to a data flow instruction mapping method utilizing the characteristics of the on-chip network inside the processor. Background technique [0002] With the development of computer architecture, the domain-specific computer architecture has become the main development trend. When facing specific applications, the special-purpose structure uses the application characteristics to optimize the structure accordingly, so as to better exert the computing performance of the hardware. In the field of high-performance computing, data flow computing is an important branch of domain-specific computing structures, and data flow computing has shown good performance and applicability. [0003] In the dataflow computing model, programs are represented as dataflow graphs. A key issue in dataflow computing is how to map dataflow graphs to multiple execution units. Datafl...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3875
Inventor 李易欧焱张浩范东睿叶笑春
Owner 上海睿伍科技有限公司
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