Display backplane and manufacturing method thereof, display panel and display device

Abstract

The invention provides a display backplane and a manufacturing method thereof, a display panel and a display device. The display backplane comprises a substrate, a first shading layer, a first thin film transistor, a first film layer and a third electrode. The first shading layer is arranged on one side of the substrate. The first thin film transistor is arranged on one side of the first shading layer away from the substrate, and includes a first active layer, a first source, a first drain and a first top gate electrode. The first film layer includes a first semiconductor part and a first conductor part, and the first semiconductor part constitutes the first active layer. The third electrode is arranged in the same layer as the first drain. The first shading layer and the first conductor part constitute a first capacitor. The third electrode and the first conductor part constitute a second capacitor. The shading layer of the display backplane not only can protect the light stability ofthe TFT structure from influence, but also can constitute a laminated pixel capacitor together with the first conductor part and the third electrode. The laminated capacitor structure can achieve high opening rate and high PPI while increasing the pixel capacitance value and improving the driving performance.

Description

technical field [0001] The present invention relates to the field of display technology, in particular, the present invention relates to a display backplane and a manufacturing method thereof, a display panel and a display device. Background technique [0002] At present, in order to improve the light-shielding effect of the top-gate thin film transistor (TFT), it is necessary to deposit a layer of metal on the glass as a light-shielding (SH) layer, and in order not to keep the layer of metal in a floating (Floating) state, it is necessary to combine the light-shielding layer with the The source end of the TFT is shorted. Although this connection scheme can meet the requirements of the bottom emission display for the normal I-V characteristics and NBTIS characteristics of the TFT, it does not have the effect of increasing the on-state current compared with the switch (Switch) TFT. [0003] For bottom emission display, it can be designed as active layer (ACT, whose potential...

AI Technical Summary

Problems solved by technology

However, the stacked capacitor structure will reduce the light-emitting area and sacrifice the aperture ratio. Therefore, this capacitor design scheme is difficult to realize for top emission displays with high PPI requirements.

[0004] Moreover, part of the test results in the current R&D stage show that the packaging process will expose the display panel (Panel) to ultraviolet (UV) environment, and the process of reliability testing will affect the uniformity of TFT characteristics, especially the light stability. Variation and other effects

However, if the SH layer is added and the design scheme of connecting the bottom-emitting SH to the TFT source is continued, the aperture ratio and high pixel count (PPI) requirements must be guaranteed, and the area of ​​the capacitor area will inevitably be compressed according to the design rules, and because the above-mentioned The multilayer capacitor design is now, so the influence of parasitic capacitance will be amplified

[0005] Therefore, the structural design of the current array substrate still needs to be improved.

Images