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Method for mixing FPGA and CPU in rail

A hybrid loading and configuration file technology, applied in the field of communication, can solve the problems of reducing utilization rate, increasing space and cost, and achieving the effect of improving reliability, saving use space and cost, and improving anti-radiation ability.

Active Publication Date: 2018-06-22
BEIJING SATELLITE INFORMATION ENG RES INST
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  • Claims
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AI Technical Summary

Problems solved by technology

[0005] The problem to be solved by the invention is that in the existing loading method, the configuration file required for loading the FPGA and the boot software for loading the CPU are respectively stored on different devices, resulting in an increase in space and cost and a problem in reducing the utilization rate

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  • Method for mixing FPGA and CPU in rail
  • Method for mixing FPGA and CPU in rail
  • Method for mixing FPGA and CPU in rail

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Embodiment Construction

[0026] Hereinafter, the present invention will be described in detail based on the drawings.

[0027] Such as figure 1 As shown, the present invention proposes a method for on-rail mixed loading of FPGA and CPU, and realizes the on-rail loading function of CPU and SRAM-type FPGA through the architecture of anti-fuse FPGA, SRAM-type FPGA, PROM, and CPU, and anti-fuse FPGA As the core of the architecture, the anti-fuse FPGA can flexibly choose to load CPU or SRAM type FPGA, and load the FPGA configuration file with the CPU configuration file.

[0028] The method of the present invention specifically comprises the steps:

[0029] Step 1. According to the requirements of SRAM-type FPGA, perform operations such as comprehensive compilation, layout and routing on FPGA through FPGA compiling software, and generate a configuration file for PROM storage and SRAM-type FPGA loading, such as *.mcs file.

[0030] Step 2, add the synchronous word command to the generated CPU boot software...

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Abstract

The present invention provides a method for mixing an FPGA and a CPU in rail. The method comprises that: an SRAM type FPGA loading configuration file is generated; the SRAM type FPGA loading configuration file and generated CPU boot software are added to the synchronization word command to be fused to generate a unified loading configuration file, and the unified loading configuration file is stored in a PROM; after power-on, the anti-fuse FPGA loads the SRAM-type FPGA according to the file read from the PROM, and after the configuration is successfully loaded, the load success signal is returned; the files are sequentially read, and when the synchronization word command in the unified loading configuration file is determined, the CPU boot software in the file is identified, the CPU is bridged to, and the booting software loading is carried out on the CPU; and the CPU autonomously generates a control signal for reading the PROM, sends the control signal to the anti-fuse FPGA, and readsback the CPU loading data from the PROM to complete loading of the CPU again. According to the method provided by the present invention, the use space and the cost of the FLASH are saved, the anti-irradiation capability of the FLASH is improved, and the reliability of the CPU configuration loading data is improved.

Description

technical field [0001] The invention belongs to the field of communication, and relates to a method for in-track mixed loading of FPGA and CPU. Background technique [0002] The CPU in space electronic products is a very important component of the electronic system, and on-orbit loading of the CPU technology is an inevitable and necessary way. With the development trend of contemporary electronic products, low cost, high integration, high reliability, and high flexibility have become the ultimate development goals. [0003] The data is lost when the CPU is powered off, and the data cannot be stored after a power failure, so an external storage device is required to store the CPU code. When powered on, read the data from the memory chip through the control chip and load it into the CPU. In the previous on-orbit loading CPU solution, it was more common to place the CPU boot software at the beginning of the high-level flash. Rely on the CPU to independently read the 4k data ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/4401
CPCG06F9/4403
Inventor 陈德沅刘宪阳王鹏程高万里崔鹤郭鹤鹤赵诣裴冬博王志勇
Owner BEIJING SATELLITE INFORMATION ENG RES INST
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