Combination device with hash partition accelerator and memory

Abstract

The invention provides a combination device containing a hash partition accelerator and a memory. The combination device comprises the memory which includes a data storage area and a logic area; the hash partition accelerator, which is integrated on the logic area of the memory and used for processing a hash join partition stage in an accelerated way, wherein the hash partition accelerator comprises a hash unit used for reading multiple tuples in a partitioned relational table from memory, and then processing keys of the multiple tuples in parallel to generate multiple hash indexes; a histogram unit used for updating a plurality of duplicates of histogram data stored in the histogram unit in parallel, and integrating each updated duplicate into a histogram data form with consistent data; and an integrating unit used for determining the position of each tuple stored in a target address array according to the multiple hash indexes, and copying the tuples in the relational table to the target array to implement the division of the relational table.

Description

technical field [0001] The present disclosure relates to the field of computer systems, and further relates to a combined device including a hash partition accelerator and a memory. Background technique [0002] The first factor to consider when designing a modern computer system is energy consumption. To improve energy efficiency, hardware accelerators such as Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs) and custom accelerators have been widely used in industry. With the advent of data-close processing technologies, integrating hardware accelerators into dynamic random access memory (DRAM) stacks to reduce the cost of data movement has become a new approach to system design. The basic idea is to use 3D stacking technology to vertically integrate some logic dies containing accelerators and multiple DRAM dies into a single chip. However, the number and types of accelerators that can be integrated into DRAMs are limited due to the area, power cons...

AI Technical Summary

Problems solved by technology

However, the number and types of accelerators that can be integrated into DRAM are limited due to the limitations of 3D stacked DRAM in terms of area, power consumption, heat dissipation, and manufacturing.

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