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3D packaging structure for mass memory circuit

A technology of large-capacity memory and packaging structure, which is applied in the direction of circuits, electrical components, semiconductor devices, etc., to achieve the effect of increasing storage capacity and meeting high reliability requirements

Inactive Publication Date: 2018-06-12
NO 47 INST OF CHINA ELECTRONICS TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In short, at this stage, it is difficult for domestic products to simultaneously meet the large-capacity and high-reliability requirements for memory products in aerospace and other fields

Method used

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  • 3D packaging structure for mass memory circuit
  • 3D packaging structure for mass memory circuit
  • 3D packaging structure for mass memory circuit

Examples

Experimental program
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Embodiment 1

[0031] In this embodiment, the flow of reliable 3D packaging of large-capacity storage circuits is as follows: figure 2 shown. The encapsulation process is as follows:

[0032] A ceramic shell is selected, the shell and the substrate are integrated, and the wiring relationship is completed inside the ceramic shell to replace the independent substrate. The memory chip is a 128Gb Nand Flash memory chip with a chip size of 11mm×15mm. First, apply a proper amount of non-conductive glue inside the tube case, and place a memory chip on the non-conductive glue inside the tube case. Next, continue to apply an appropriate amount of non-conductive glue on the memory chip, and place another memory chip on the non-conductive glue on the memory chip.

[0033] Staggered bonding between the memory chip and the memory chip. After the two chips are vertically aligned and the centers coincide, the second chip moves horizontally 2mm along the X\Y direction to expose the PAD point of the firs...

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PUM

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Abstract

The invention discloses a 3D packaging structure for a mass memory circuit, and belongs to the technical field of electronic product packaging. The structure comprises memory chips, an adhesive, bonding wires, a substrate, and a housing. The structure comprises a plurality of memory chips, and the memory chips form a 3D chip group in a vertically staggered and stacked manner, wherein the memory chips are bonded through the adhesive. The 3D chip group is bonded on the substrate through the adhesive, and the substrate is fixed on the housing through the adhesive. The bonding wires are used for forming the electrical connection between the 3D chip group and the substrate, between the 3D chip group and the housing, and between the memory chips. According to the invention, the chips are arranged in the vertically staggered and stacked manner, thereby enlarging the capacity and meeting the high-reliability of a memory product in domestic cutting-edge industries.

Description

technical field [0001] The invention relates to the technical field of packaging of electronic products, in particular to a 3D packaging structure of a large-capacity memory circuit. Background technique [0002] Memory circuits are widely used in space data storage, high-end electronic countermeasures, network information security, distributed computing, high-speed data acquisition, big data storage, industrial intelligence and other fields, especially on satellites and rockets, for large-capacity, high-reliability memory Circuits are in increasing demand. my country's memory circuit products are generally based on single-chip packaging or multi-chip 2D packaging. The ratio of effective storage capacity to packaging area is not high, which cannot meet the needs of cutting-edge industries for large-capacity storage. Some packaging manufacturers adopt the method of multi-chip 3D stack packaging, which can greatly increase the ratio of storage capacity to packaging area, but ...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L25/065
CPCH01L25/065H01L23/31H01L2224/48147
Inventor 赵鹤然
Owner NO 47 INST OF CHINA ELECTRONICS TECH GRP
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