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Semiconductor device and manufacturing method thereof, and electronic device including same

A technology for semiconductors and devices, applied in the fields of vertical semiconductor devices and their manufacture, and electronic equipment, can solve the problems of difficulty in further reducing the area of ​​horizontal devices, shrinking the area of ​​horizontal devices, increasing power consumption and resistance, etc. Risk of lithography misalignment, reduced manufacturing cost, reduced effect of lithography steps

Active Publication Date: 2018-06-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to this arrangement, reducing the area occupied by the horizontal device generally requires the area occupied by the source, drain and gate to be reduced, which deteriorates the performance of the device (for example, increased power consumption and resistance), so the horizontal device Difficult to further reduce the area

Method used

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  • Semiconductor device and manufacturing method thereof, and electronic device including same
  • Semiconductor device and manufacturing method thereof, and electronic device including same
  • Semiconductor device and manufacturing method thereof, and electronic device including same

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Embodiment Construction

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0014] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, ...

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Abstract

The invention discloses a semiconductor device. The semiconductor device includes a substrate; a vertical active area formed on the substrate, wherein the vertical active area includes a first source / drain region, a channel region, and a second source / drain region, and the first source / drain region includes a horizontal extension portion extending out of the active area above the first source / drain region; gate stack formed on an outer periphery of the channel region, wherein the gate stack includes a horizontal extension portion; a stack contract portion from a position above the horizontal extension portion of the first source / drain region to the horizontal extension portion of the first source / drain region, wherein the stack contact portion includes three structures which are vertically and successively arranged; and the three structures include a lower portion, an intermediate portion, and an upper portion, wherein the lower portion at least includes elements identical to elements forming the first source / drain region, the intermediate portion at least includes elements identical to elements forming the channel region, and the upper portion at least includes elements identical to elements forming the second source / drain region.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and in particular, to a vertical type semiconductor device, a method of manufacturing the same, and an electronic device including such a semiconductor device. . Background technique [0002] In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, reducing the area occupied by the horizontal device generally requires the area occupied by the source, drain and gate to be reduced, which deteriorates the performance of the device (for example, increased power consumption and resistance), so the horizontal device The area is not easy to further reduce. Unlike this, in a vertical type device, the source, gate, and drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, compar...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66666H01L29/7827H01L29/665H01L29/7843H01L29/161H01L29/165H01L29/7848H01L29/66545H01L21/2255H01L29/66356H01L29/1033H01L29/0847H01L29/7391H01L21/3065H01L21/308H01L21/823418H01L21/823475H01L21/823487H01L27/088H01L29/41741H01L29/45H01L29/66977
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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