FPGA online upgrading method based on NIOS II

Abstract

The invention relates to the field of FPGA chips, and discloses an FPGA online upgrading method based on NIOS II. An FPGA can be reconfigured without the assistance of external controller chips underan AS configuration mode online. An IP of a NIOS II processor is embedded into the FPGA to serve as a controller, and an external serial port and an internet access are integrated; when the system iselectrified or reset, the NIOS II processor starts a locator, a waterdog program is closed, if the data NIOS II processor does not receive data from the serial port or the internet access within a limited time, then FPGA configured file data is read from a configured FLASH chip, and then the system enters a user mode; if the data is received and is upgraded data, then the upgraded data is writteninto the configured FLASH chip, the watchdog program is started after the upgraded data is received and written, system restoration is triggered, and online upgrading of the FPGA is completed. The FPGA online upgrading method is applicable to FPGA configuration.

Description

technical field [0001] The invention relates to the field of FPGA chips, in particular to an FPGA online upgrade method based on NIOS II. Background technique [0002] FPGA has the characteristics of flexible programming and can be used as a development platform for the prototype design of special satellite navigation chips. The configuration data of the FPGA based on the SRAM process will be lost after power-off, and an external configuration FLASH chip is needed to save the FPGA configuration data, such as EPCS64, EPCQ256, etc. After power-on, the configuration data stream needs to be read from the configuration FLASH chip and loaded into the FPGA, so that the FPGA can run normally. [0003] Commonly used FPGA configuration methods include active serial mode (AS) and passive serial mode (PS). In AS mode, FPGA provides configuration clock signal DCLK, and in PS mode, other devices provide configuration clock signal DCLK to FPGA. AS configuration mode box figure 1 shown. ...

AI Technical Summary

Problems solved by technology

[0006] In the existing AS configuration mode, the JTAG port of the FPGA needs to be connected every time the FPGA is upgraded. After the FPGA is integrated into the entire system, the JTAG port is usually not reserved for the external interface of the system, and it needs to be disassembled when upgrading, which is time-consuming and laborious.

The existing PS configuration mode can reconfigure FPGA through the external interface of the system such as serial port and network port, which solves the problem of inconvenient upgrade in AS mode

However, at present, the density of FPGA is increasing, and the configuration data is also increasing, reaching tens of megabits or even hundreds of megabits. Multiple flash chips are required to store these configuration data, resulting in increased complexity and additional hardware costs, such as FLASH chip and controller chip cost

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