A memory access method and computer system

Abstract

A memory access method, used to decrease memory access latency, said method comprising: a memory controller acquiring a second access request in an access queue (408), said access queue at least comprising a first access request and said second access request, the second access request comprising a second row address and a second column address; the memory controller determining that the second row address hits a second address range (409), the row indicated by a third row address in the second address range being in an activated state, and the second row address and the third row address being different; the memory controller sending a second access instruction to a control circuit according to the second access request (410), the second access instruction including the second column address and a second row offset, the second row offset being the offset amount between the second row address and the third row address.

Description

technical field [0001] The invention relates to the communication field, in particular to a memory access method and a computer system. Background technique [0002] In an existing computer system, the memory is usually composed of Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory). In the case of a memory composed of a non-volatile memory (NVM), the NVM is connected to a standard Double Data Rate (DDR) bus. In NVM, there is a part of the register space that can be accessed by the memory controller through the Double Data Rate (DDR) bus. The register space usually includes: configuration register space, request completion queue, request queue, data buffer, etc. [0003] In the case of NVM as a memory, in the process of accessing the NVM by the memory controller, the access method of accessing the DRAM is usually used to access the registers of the NVM. Specifically, during the access process, the memory controller needs to send row activation commands and co...

AI Technical Summary

Problems solved by technology

Since the memory controller needs to send an activation command to process each access request, the access delay in the memory access process is large and the access efficiency is not high

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