A system-level chip production method with fault diagnosis

Abstract

The invention provides a system-on-a-chip (SoC) production method with fault diagnosis. The method comprises the steps of providing a pre-processed composite structure; arranging a metal pad on the pre-processed composite structure; arranging a plurality of metal bumps and a plurality of registers on a probe card, each register being connected with the respective metal bump, the plurality of registers forming a boundary-scan chain, and pressing the probe card on the pre-processed composite structure; completing a fault diagnosis by using a test access port controller to obtain relevant information to a faulty kernel circuit module, then removing the probe card and connecting a plurality of kernel circuit modules; and packaging the pre-processed composite structure. The method of the invention has the beneficial effects of saving the chip area, testing during the manufacturing process, enabling the chip manufacturing to complete the test and discovery in advance, reducing the searchingscope, realizing online positioning of manufacturing defects, reducing the test complexity, and improving the chip testing efficiency, and fault diagnosis coverage and fault diagnosis accuracy.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a system-level chip production method with fault diagnosis. Background technique [0002] The basic idea of ​​boundary scan technology is to add a shift register unit on the input and output pins close to the chip. Because these shift register units are distributed on (around) the boundary of the chip, they are called boundary-scan registers (Boundary-Scan Register Cell, BSR). [0003] When the chip is in the debugging state, these boundary scan registers can isolate the input and output of the chip and the periphery. Through these boundary scan register units, the observation and control of the input and output signals of the chip can be realized. For the input pin of the chip, the signal (data) can be loaded into the pin through the connected boundary scan register unit; for the output pin of the chip, it can also be "captured" through the connected boundary scan ...

AI Technical Summary

Problems solved by technology

[0007] However, since multiple shift registers for fault diagnosis are set in the chip, the chip is larger in size; with the improvement of circuit integration and circuit complexity, it becomes more and more difficult to improve the fault coverage rate during fault diagnosis. The cost of testing using automatic test equipment is getting higher and higher; at the same time, the development cycle and fault location have become project bottlenecks

Images