Successive Approximation Analog-to-Digital Converter Based on Asymmetric Differential Capacitor Array

A successive approximation, analog-to-digital converter technology, applied in the direction of analog/digital conversion, code conversion, instruments, etc., can solve the problems of increased power consumption and low precision, so as to save capacitance and area, and reduce capacitance area , The effect of reducing power consumption

Active Publication Date: 2020-09-25
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the traditional successive approximation analog-to-digital converter based on capacitor array, due to the relatively large area of ​​the capacitor array, the accuracy cannot be achieved very high, and it will cause the problem of increased power consumption

Method used

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  • Successive Approximation Analog-to-Digital Converter Based on Asymmetric Differential Capacitor Array
  • Successive Approximation Analog-to-Digital Converter Based on Asymmetric Differential Capacitor Array
  • Successive Approximation Analog-to-Digital Converter Based on Asymmetric Differential Capacitor Array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] See figure 1 , figure 1It is a logical schematic diagram of a successive approximation analog-to-digital converter based on an asymmetrical differential capacitor array provided by an embodiment of the present invention. The successive approximation analog-to-digital converter based on the asymmetric differential capacitor array of this embodiment includes a sample-and-hold circuit 11 , a comparator 12 and a logic control module 13 . The sample-and-hold circuit 11 includes an asymmetric differential capacitor array 110 and a sampling switch module 111, wherein the first input terminal of the asymmetric differential capacitor array 110 is selectively electrically connected to the common-mode voltage terminal Vcm and the ground terminal through the single-pole double-set switch S3 gnd, the second input terminal of the asymmetric differential capacitor array 110 is electrically connected to the output terminal of the sampling switch module 111, the third input terminal of...

Embodiment 2

[0043] See image 3 , image 3 It is a schematic structural diagram of an n-capacitor array provided by an embodiment of the present invention.

[0044] Such as image 3 shown, the n-capacitor array C n Including an N-1-bit upper capacitor group C connected in parallel between the sampling switch S2 and the second single-pole double-setting switch S32 0 up,n to C N-2 up,n and N-1 lower capacitor bank C 0 down,n to C N-2 down,n , where, N-1 upper capacitor group C 0 up ,n to C N-2 up,n Capacitor bank C on bit 0 0 up,n and the 1st upper capacitor bank C 1 up,n Both include a capacitor unit, the capacitance values ​​are C and 2C respectively; the capacitor group C on the N-2 position N-2 up,n It is a binary capacitor group, including N-2 capacitor units, and the capacitance value of the N-2 capacitor units is 2 N-3 C....4C, 2C, 2C, where N≧4. It is worth noting that the 2nd upper capacitor bank C 2 up,n To the N-2th upper capacitor group C N-2 up,n The c...

Embodiment 3

[0056] Please also see Figure 5 to Figure 8 , Figure 5 to Figure 8 It is a working principle diagram of an asymmetric differential capacitor array applied to a 4-bit successive approximation analog-to-digital converter provided by an embodiment of the present invention. This embodiment takes a 4-bit successive approximation analog-to-digital converter as an example to specifically illustrate the working principle of the successive approximation analog-to-digital converter based on the asymmetric differential capacitor array of the present invention.

[0057] (1) The analog input signals SVip and SVin are held by the sample-and-hold circuit 11, and the p-capacitor array C p The connection mode of the upper capacitor is (gnd, gnd), and the connection mode of the lower capacitor is (Vcm, Vcm); the n capacitor array C n The connection mode of the upper capacitor is (gnd, gnd, gnd, gnd), and the connection mode of the lower capacitor is (Vcm, Vcm, Vcm, Vcm). After sampling, th...

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Abstract

The invention relates to a successive approximation register analog-to-digital converter based on an asymmetric differential capacitor array. The successive approximation register analog-to-digital converter comprises a sample hold circuit, a comparer and a logic control module. The sample hold circuit comprises an asymmetric differential capacitor array and a sample switch module. According to the asymmetric differential capacitor array, a first input end is selectively electrically connected with a common-mode voltage end and a grounding terminal through a single pole double throw switch, asecond input end is electrically connected with an output end of the sample switch module, a third input end is electrically connected with a first output end of the logic control module, and the output end is electrically connected with the comparer. The first input end and the second input end of the sample switch module are electrically connected with an analog signal negative input end and ananalog signal positive input end. The output end of the comparer is electrically connected with the input end of the logic control module. According to the successive approximation register analog-to-digital converter provided by the invention, the power consumption can be effectively reduced, a capacitor area can be reduced, and the design difficulty can be reduced.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a successive approximation analog-to-digital converter based on an asymmetric differential capacitance array. Background technique [0002] At present, with the promotion of wearable devices and the development of precision biological instruments, successive approximation analog-to-digital converters are widely used because of their simple structure and low power consumption. Since the successive approximation analog-to-digital converter does not require linear gain blocks such as operational amplifiers, it can better adapt to the process evolution trend of feature size reduction and power supply voltage reduction. With the advancement of technology, the conversion rate that can be achieved by successive approximation analog-to-digital converters has increased to hundreds of megabytes, which can be compared with pipeline-type analog-to-digital con...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/00H03M1/38
CPCH03M1/002H03M1/38
Inventor 朱樟明于哲刘术彬丁瑞雪
Owner XIDIAN UNIV
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