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Method of growth morphology and component control over plane germanium silicon and relative nanowires based on heterogeneous laminated amorphous film supply

A technology of amorphous thin film and nanowire, which is applied in the direction of nanotechnology, nanotechnology, nanostructure manufacturing, etc., can solve the problem of low compatibility of standard silicon processes, limitations of large-scale device integration of VLS nanowires, and functional applications, micro High operating costs and other issues

Active Publication Date: 2018-01-30
NANJING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these micro-nano operations are expensive and not compatible with standard silicon processes, especially the large-scale controllable positioning integration technology of nanowires has been difficult to break through
This also greatly limits the large-scale device integration and functional application of VLS nanowires.

Method used

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  • Method of growth morphology and component control over plane germanium silicon and relative nanowires based on heterogeneous laminated amorphous film supply
  • Method of growth morphology and component control over plane germanium silicon and relative nanowires based on heterogeneous laminated amorphous film supply
  • Method of growth morphology and component control over plane germanium silicon and relative nanowires based on heterogeneous laminated amorphous film supply

Examples

Experimental program
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Effect test

Embodiment 1

[0028] Example 1, In (indium)-induced growth of germanium-rich junction region ~ 160nm diameter ~ 40nm silicon germanium wire, Ge (germanium) content periodically changes the method for directional growth of germanium-enriched island-shaped planar silicon-germanium heterojunction nanowires .

[0029] A 500 μm silicon-based substrate with a silicon dioxide layer thickness of 300 nm was used to obtain a clean substrate through an RCA standard cleaning process.

[0030] 1) A photolithographic sample with a corresponding pattern was prepared using a photolithographic plate with a strip width of 3 μm and a spacing of 3 μm. After ICP etching to a depth of ~150 nm, it was cleaned with acetone, and the photoresist was washed away before secondary photolithography was performed. The second photolithography is perpendicular to the photolithographic pattern obtained by ICP etching, and a photolithographic sample with a strip width of 10 μm and a strip spacing of 100 μm is prepared. A 30...

Embodiment 2

[0034] Example 2, Sn (tin) induced growth of germanium-rich junction region ~ 160nm diameter ~ 40nm silicon germanium wire, Ge (germanium) content periodically changes the method for directional growth of germanium-enriched island-shaped planar silicon-germanium heterojunction nanowires .

[0035] A 500 μm silicon-based substrate with a silicon dioxide layer thickness of 300 nm was used to obtain a clean substrate through an RCA standard cleaning process.

[0036] 1) A photolithographic sample with a corresponding pattern was prepared using a photolithographic plate with a strip width of 3 μm and a spacing of 3 μm. After ICP etching to a depth of ~150 nm, it was cleaned with acetone, and the photoresist was washed away before secondary photolithography was performed. The second photolithography is perpendicular to the photolithographic pattern obtained by ICP etching, and a photolithographic sample with a strip width of 10 μm and a strip spacing of 100 μm is prepared. A 30 nm...

Embodiment 3

[0040] Example 3, In, Sn (indium, tin alloy) induced growth germanium-rich junction region ~ 160nm diameter ~ 40nm silicon germanium line, Ge (germanium) content periodically changes direction growth germanium-enriched island-shaped planar silicon-germanium heterogeneity Methods for knotting nanowires.

[0041] A 500 μm silicon-based substrate with a silicon dioxide layer thickness of 300 nm was used to obtain a clean substrate through an RCA standard cleaning process.

[0042] 1) A photolithographic sample with a corresponding pattern was prepared using a photolithographic plate with a strip width of 3 μm and a spacing of 3 μm. After ICP etching to a depth of ~150 nm, it was cleaned with acetone, and the photoresist was washed away before secondary photolithography was performed. The second photolithography is perpendicular to the photolithographic pattern obtained by ICP etching, and a photolithographic sample with a strip width of 10 μm and a strip spacing of 100 μm is prep...

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Abstract

The invention provides a method for preparation of heterogeneous or alloy semiconductor nanowires by means of a laminated amorphous precursor layer. With the silicon germanium system as an example, amorphous silicon (a-Si) / amorphous germanium (a-Ge) laminated film is used as the precursor, the silicon germanium chain nanowire structure of spontaneous phase separation is prepared, the laminated layer amorphous film is used as the precursor layer, through absorption of metal droplets and the plane nanowire growth process, plane silicon germanium nanowires of spontaneous phase separation are achieved, its morphology can be controlled through the thickness of the laminated layer and the laminated sequence, and the silicon germanium chain structure is regulated; when the amorphous germanium layer is on the bottom of the a-Si / a-Ge structure, the wide area of the silicon and germanium nanowires is the high-concentration area of germanium, while the thin nanowires are connected to a high-concentration area of silicon; or the silicon germanium alloy nanowire structure with a uniform diameter is achieved by the reverse laminated sequence, or the silicon-germanium alternate area structure including microzone intervals is formed.

Description

1. Technical field [0001] The invention relates to the key technology of micro-nano preparation and component regulation of semiconductor nanowire / channel structure. Emphasize the use of composite stacked amorphous stacks as the precursor supply layer, directly grow germanium-silicon alloys and heterogeneous self-nested nanowire structures on planar substrates, and spontaneously realize island chain morphology control and silicon-germanium island chain phase separation, etc. core controls. In the silicon germanium material system, the addition of germanium components can increase the hole mobility of the crystalline silicon channel, thereby greatly improving device performance. This technology has broad and important application prospects in photoelectric detection, thermoelectric conversion, high-performance flat-panel display thin-film transistors, single-electron devices, and low-dimensional photonic crystals. 2. Technical background [0002] Silicon-based materials hav...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B82B3/00B82Y40/00
Inventor 余林蔚赵耀龙王军转
Owner NANJING UNIV
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