Capacitance multiplier with high multiplication constant

Abstract

The invention discloses a capacitance multiplier with a high multiplication constant; the capacitance multiplier comprises a first cascode circuit module, a second cascode circuit module, a trsanscondutance amplifier circuit module, an on-chip capacitor, a first bias current source, a second bias current source and a third bias current source; the trsanscondutance amplifier circuit module is provided with a first input end and a second input end, wherein the first input end is connected with the first cascode circuit module output end, the second input end is connected with the second cascodecircuit module output end, and the trsanscondutance amplifier circuit module output end is connected with the on-chip capacitor; the high output impedance adjusting type cascode circuit structure is employed, and a current mirror structure is added on the trsanscondutance amplifier circuit module output end, thus greatly improving the capacitance multiplier multiplication constant, and forming a greater equivalent on-chip capacitor. The whole capacitance multiplier circuit structure only uses a CMOS transistor and the capacitor, is small in area, and high in multiplication constant.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a capacitance multiplier with a high multiplication factor. Background technique [0002] As a basic electronic component, capacitors are widely used in various analog circuits. For example, loop filters, low-dropout linear regulators, AC-DC, DC-DC converters, etc., often require large capacitors on the order of tens of nF or tens of μF. If a capacitor of this magnitude is integrated in the chip, it will inevitably occupy a very large on-chip area; if an off-chip capacitor is used, additional pins are required, which also increases the area of ​​the printed circuit board (PCB) and the difficulty of design , at the same time, the added pins may also introduce new parasitic parameters, which will further affect the circuit performance. [0003] Using on-chip active devices to construct a capacitance multiplication circuit to realize the on-chip equivalent large capaci...

AI Technical Summary

Problems solved by technology

However, in this circuit structure, the multiplication factor of the capacitance depends on the ratio of the transistor size and the current ratio between the current mirrors. Excessively high current multiplication coefficients will inevitably lead to an increase in circuit power consumption, so this circuit structure is not suitable for high multiplication factors. The design of the capacitance multiplier

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