A method for data interaction between multi-core processor cores based on delay compensation

A multi-core processor and data interaction technology, which is applied in the direction of electrical digital data processing, instruments, digital computer components, etc., can solve the problems of low certainty of data interaction time and lack of engineering application value in the field of industrial control, etc.

Active Publication Date: 2020-06-09
NANJING GUODIAN NANZI POWER GRID AUTOMATION CO LTD
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  • Abstract
  • Description
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Problems solved by technology

However, in the implementation of this invention, the interrupt response delay and task response delay of the receiving core are not taken into consideration, so the time certainty of data interaction between cores is not high, and it does not have the actual industrial control field engineering Value

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  • A method for data interaction between multi-core processor cores based on delay compensation
  • A method for data interaction between multi-core processor cores based on delay compensation
  • A method for data interaction between multi-core processor cores based on delay compensation

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Embodiment Construction

[0042] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0043] The application principle of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0044] An important purpose of intra-kernel communication is to send data from one core to the data processing core for processing. When the data is ready, the sending core usually notifies the receiving core through an inter-core interrupt inside the processor. The interrupt response time of the receiving core is also an important data transmission delay.

[0045] At present, there are already many high-real-time operating systems that can control the interrupt response delay to about...

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Abstract

The invention discloses a multi-core processor inter-core data interaction method based on time delay compensation. Data is transmitted by a sending core, and the sending core triggers a timer in a processor to start counting; after the sending core completes data sending, an interrupting controller triggers the internal interrupting of a receiving core; the receiving core responds to the internalinterrupting by means of an interrupting processing function, and a task scheduler is informed to activate a receiving task. When inter-core data is received after the receiving task is activated, the count number of the timer triggered by the sending core is read and the timer is reset. The time delay from the transmission to the completion of receiving of the receiving task of the data is obtained through counting of the timer, the time delay compensation of the data is conducted on the basis of the time delay, the interlocking of shared resource access and the precise calculating of the processor inter-core communication time delay are avoided, and the high-time-accuracy data interaction is achieved.

Description

technical field [0001] The invention specifically relates to a method for data interaction between multi-core processor cores based on delay compensation. Background technique [0002] With the rapid development of network and computer technology, the performance requirements of processors are getting higher and higher. The means of improving the single-core performance of the processor is mainly to increase the operating frequency of the processor. When the processor is already working at a higher frequency, it becomes very difficult to increase the operating frequency of the processor. Therefore, there is an invisible performance upper limit for the performance improvement of the processor when there is no breakthrough in processor technology. In order to overcome this invisible performance upper limit, the improvement of the overall performance of the processor is increasingly dependent on adding multiple processor cores to work together in a processor, so that the proce...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/167G06F15/173
Inventor 潘可叶品勇余华武
Owner NANJING GUODIAN NANZI POWER GRID AUTOMATION CO LTD
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