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Digital-analog hybrid control multi-loop LDO circuit

A digital-analog hybrid, multi-loop technology, applied in control/regulating systems, regulating electrical variables, instruments, etc., can solve the problem of low load transient response capability of LDO circuits, and achieve the effect of improving load response speed

Active Publication Date: 2017-12-19
FOSHAN UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The LDO circuit with this structure has the problem of low load transient response capability

Method used

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  • Digital-analog hybrid control multi-loop LDO circuit
  • Digital-analog hybrid control multi-loop LDO circuit
  • Digital-analog hybrid control multi-loop LDO circuit

Examples

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Embodiment 1

[0014] Embodiment 1, reference figure 2 , a digital-analog hybrid control multi-loop LDO circuit, comprising: power tube M P , pMOS transistors M1, M3, M5, nMOS transistors M2, M4, M6, M7, M8, operational amplifiers AMP, NOT gates INV1, INV2, INV3, INV4, INV5, INV6, AND gates AND1, AND2, the pMOS transistor M1 , M3, power tube M P The sources of are respectively connected to the power supply VDD, as an optimization, where the power tube M P A pMOS transistor is used, the gate of the pMOS transistor M1 is connected to the output terminal of the inverting gate INV3, the input terminal of the inverting gate INV3 is connected to the output terminal of the AND gate AND2, and an input of the AND gate AND2 end is connected with the output terminal of the NOT gate INV4, the other input terminal of the AND gate AND2 is connected with the input terminal of the NOT gate INV4 and the output terminal of the NOT gate INV5 respectively, and the input terminal of the NOT gate INV4 end is ...

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Abstract

The invention discloses a digital-analog hybrid control multi-loop LDO circuit. The digital-analog hybrid control multi-loop LDO circuit comprises a power tube MP, pMOS tubes M1, M3 and M5, nMOS tubes M2, M4, M6, M7 and M8, an operational amplifier AMP, NOT gates INV1, INV2, INV3, INV4, INV5 and INV6 and AND gates AND1 and AND2. The LDO circuit disclosed by the invention utilizes three control loops for dealing with change of load voltage, load transient state response capability is provided, and through simulation, the load transient state response capability of the LDO circuit disclosed by the invention is improved by 10% compared with that of an existing LDO circuit. The LDO circuit disclosed by the invention can be widely applied to SoC.

Description

technical field [0001] The invention relates to a system for adjusting electric or magnetic variables, in particular to an LDO (Low Dropout Regulator, LDO, low dropout linear regulator) circuit. Background technique [0002] Almost all electronic circuits require a stable voltage source that is maintained within certain tolerances for proper operation (a typical CPU circuit only allows the voltage source to deviate from the rated voltage by no more than ±3% maximum). This fixed voltage is provided by some kind of voltage regulator. The LDO circuit is one of the regulators. [0003] like figure 1 As shown, the current LDO circuit includes: a reference voltage Vref, an error amplifier EA, a power transistor a1, a resistor divider a2, and a current source a3. The LDO circuit automatically detects the output voltage Vout through the resistor divider a2, and the error amplifier EA constantly adjusts the current source a3 so as to maintain the output voltage Vout at the rated v...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/56
CPCG05F1/561
Inventor 段志奎王志敏陈建文于昕梅樊耘李学夔朱珍王东
Owner FOSHAN UNIVERSITY
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