A chip double-sided vertical packaging structure and packaging method

Abstract

The invention relates to the technical field of semiconductor manufacturing, and especially relates to a chip double-side vertical packaging structure and a packaging method. After a PCB structure with a conductive material layer is prepared, a chip is bonded onto the conductive material in a bonding area of the PCB structure. After a first solder layer is formed on the back of the PCB structure, the chip is plastically packaged with a plastic package material, the plastic package material is windowed, and a second solder layer is formed in the window. Therefore, ultra-thin and high-performance vertical chip package is realized under the condition of minimum size. The chip double-side vertical packaging structure has the advantages of small size and high reliability.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a chip double-sided vertical packaging structure and packaging method. Background technique [0002] At present, chip packaging technology is constantly pursuing the development of thinness, miniaturization, portability, high reliability, low power consumption and low cost. [0003] Traditional common chip mainstream packaging forms are roughly divided into: lead frame type, such as DIP (Dual In-line Package, dual in-line package), SOP (Small Outline Package, small size package), QFN (QuadFlatNo-lead Package, square Flat leadless package) and QFP (Plastic Quad Flat Package, square flat package), etc.; ball grid array type, such as: BGA (Ball Grid Array Package, ball grid array package), FC-BGA (FlipChip BGA, flip chip technology ball grid array package) and μBGA, etc., these packaging methods need to connect the poles of the chip to the external pins and fram...

AI Technical Summary

Problems solved by technology

[0003] Traditional common chip mainstream packaging forms are roughly divided into: lead frame type, such as DIP (Dual In-line Package, dual in-line package), SOP (Small Outline Package, small size package), QFN (QuadFlatNo-lead Package, square Flat leadless package) and QFP (Plastic Quad Flat Package, square flat package), etc.; ball grid array type, such as: BGA (Ball Grid Array Package, ball grid array package), FC-BGA (FlipChip BGA, flip chip technology ball grid array package) and μBGA, etc., these packaging methods need to connect the poles of the chip to the external pins and frames through leads, or directly connect and bond with the pins and frames, so that the volume of the final package is often It is several times larger than the chip itself, especially in the vertical direction, the thickness is relatively large, and there is a large stress distribution inside the packaged product, and at the same time, it is easy to produce relatively uneven upper and lower contact surfaces, resulting in low online accuracy. Problems limit the application on ultra-thin electronic systems (such as electronic smart wearable devices, etc.), which is not expected by those skilled in the art

Images