Array substrate and preparation method thereof, display panel and display device
A technology for array substrates and display panels, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, and electrical solid-state devices, etc., can solve problems such as reducing the aperture ratio of display devices and affecting the display quality of display panels.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
preparation example Construction
[0049] Based on the same inventive concept, an embodiment of the present invention also provides a method for preparing an array substrate, such as Figure 4 shown, including:
[0050] S401, forming a driving transistor and a switching transistor on a base substrate, and forming a pattern of a first electrode of a first capacitor, wherein the first electrode of the first capacitor is respectively connected to a gate electrode of the driving transistor and a source electrode of the switching transistor;
[0051] S402, forming a pattern of a passivation layer covering the first electrode of the first capacitor, and the passivation layer is provided with a groove and a via hole penetrating through the passivation layer in a region corresponding to the first electrode of the first capacitor;
[0052] S403, forming a pattern of the second electrode of the first capacitor in the groove, and connecting the second electrode of the first capacitor to the source of the driving transisto...
Embodiment 1
[0056] Taking an array substrate including 3 transistors and 1 capacitor as an example, the preparation method of the array substrate specifically includes:
[0057] 1. A gate electrode 9, a gate insulating layer 5, an active layer 10, an etching stopper layer 6, a drain electrode 11 or a source electrode 12, and a passivation layer 3 are sequentially formed on the base substrate 4 through a patterning process, such as Figure 5a shown;
[0058] 2. Coating photoresist 16 above the passivation layer 3, such as Figure 5b shown;
[0059] 3. Irradiating the photoresist 16 with a half-tone mask or a gray-tone mask to form a via area corresponding to the I region and a groove region corresponding to the II region on the photoresist 16, wherein the half-tone mask The slab or gray tone mask includes a transparent area I, a semi-transparent area II and a light-shielding area III, such as Figure 5c shown;
[0060] 4. Form a via hole 14 penetrating through the passivation layer at ...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com