3D NAND memory device and manufacturing method therefor

Abstract

The invention provides a 3D NAND memory device. The memory device comprises a substrate, a first memory region, a sub step region, run-through contact holes, and grid line gaps, wherein the first memory region is arranged on the substrate; the first memory region comprises a word line stacking layer and channel holes in the word line stacking layer; the side wall of the word line stacking layer adopts a step structure; the sub step region is arranged in the step structure; the sub step region is a stacked layer of an oxide layer and a nitride layer; the sub step region extends to the edge of the step structure in a word line direction; an insulating layer is arranged on the side wall, connected with the step structure, of the sub step region; the run-through contact holes are formed in the sub step region; and the grid line gaps are formed in the step structure outside the sub step region. By virtue of the run-through contact holes with the structure, connection between the memory device and a CMOS chip can be realized conveniently, and the memory device can be integrated with the existing process easily; particularly, when the thickness of the stacking layer is constantly increased, a step of etching metal stacking to form the run-through contact holes is not needed, so that realization of the process and constant improvement of the integration degree can be facilitated.

Description

technical field [0001] The invention relates to the field of flash memories, in particular to a 3D NAND memory device and a manufacturing method thereof. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An array ...

AI Technical Summary

Problems solved by technology

[0003] In the 3D NAND memory structure, the stacked 3D NAND memory structure is realized by stacking multiple layers of data storage units vertically. However, other circuits such as decoder, page buffer and latch ), etc., these peripheral circuits are all formed by CMOS devices, and the technology of CMOS devices cannot be integrated with 3D NAND devices. An array of vias electrically connects the two together

The stacking in the 3D NAND memory array mainly adopts the OPOP structure, that is, the structure in which polysilicon (poly) and oxide (oxide) are stacked in sequence. With the continuous improvement of storage capacity requirements, the number of stacked layers of the OPOP structure is increasing. The formation of

Images