A built-in self-test design method for multiple embedded memories on a single chip

Abstract

The invention discloses a built-in self-test designing method of multiple embedded memories on single chip. In the method, reasonable memory built-in self-test scheme and structure are determined according to the working frequency, size, port type, number and layout of memories on a chip; in design, multiple memory built-in self-test logics are inserted, a test way of multiple combinations of serial and parallel tests is realized, the test time, test cost, test power consumption and area increase of test logics of the memories are optimized, the test efficiency is improved, and the layout wiring and timing closure in layout design are facilitated; a clock selection logic circuit is added to realize high-speed test and low-speed test; and moreover, with additional bypass logic of the memory, the loss of test coverage in a digital logic scanning test caused by the memory shadow logic can be eliminated, and the test coverage is increased.

Description

technical field [0001] The invention relates to a design method of Memory Built-In Self Test (MBIST) of multiple embedded memories on a single chip, especially the MBIST design when the working frequency of each memory differs greatly and the layout positions are far apart. The method belongs to the field of semiconductor digital integrated circuit design and testing, and is mainly applied to the MBIST design process of on-chip embedded memory of the semiconductor digital integrated circuit. Background technique [0002] With the development of integrated circuits, the integration level of chips has increased rapidly, and the proportion of embedded memory in the entire chip is increasing. The use of faster and larger on-chip memories is an inevitable development trend in the future. The method of testing memory based on functional vectors is not accepted by chip design manufacturers due to the constraints of test difficulty, test coverage and test efficiency. At present, th...

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Problems solved by technology

[0003] Since the number of integrated memories in previous chips is not very large, and the memory test logic itself will occupy a certain area and power consumption, the traditional method is to use a controller to perform the MBIST test of all memories; at the same time, the memory test clock adopts the same function clock In the form of multiplexing, it is impossible to achieve flexible control of the MBIST test clock; in addition, during the scan test, since the output of the memory is uncontrollable, it is a loss for the scan test coverage, which will lead to a decrease in the scan test coverage. reduce

[0004] At present, a single chip has rich functions in many cases, and a large number of block-type memories are often integrated inside the chip to realize different data or program storage functions, and are arranged in different positions of the chip. If only inserting One controller will make the test time of all the memories of the whole chip very long, especially in the products supplied in large quantities, making the test cost unacceptable, and causing the wiring process of the layout design to have too long winding problems that make timing difficult to close

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