A method for dual-core shared output peripherals of Zynq chip in heterogeneous multi-processing mode

Abstract

The invention provides a method for outputting a peripheral through dual core sharing of a Zynq chip in an asymmetric multi-processing mode. An FPGA distributes shared memories with different service priorities to ARM cores, when the ARM cores have to-be-transmitted messages, firstly, information of the shared memories with the FPGA is read, under the judged writable condition, data packages and data package description information are written in the shared memories according to a stipulated format, and under the condition that the FPGA judges peripheral transmitting idling, the data packages in the shared memories are written in the peripheral according to the service priorities. The peripheral and data package scheduling is managed uniformly by the FPGA, no internuclear scheduling is needed between the double ARM cores, each ARM core independently deals with the FPGA peripheral, and efficiency is greatly improved compared with uniform data management and transmitting in an ARM. The method is used for the power system control field with the large data throughout and high processing real-time-performance requirements.

Description

technical field [0001] The invention belongs to the field of electric power system control, and is suitable for requiring less device space, requiring the use of a single-chip multi-core processor, and simultaneously supporting high processing real-time performance and man-machine interface, etc., which require multiple services such as file systems and network protocols. Background technique [0002] With the continuous development and progress of substation automation technology, the requirements for high-speed data throughput of various automation equipment in smart substations are rapidly increasing. [0003] Based on the ARM processing core and the Advanced Microprocessor Bus Architecture (AMBA) bus definition, the FPGA manufacturer Xilinx uses the high-speed parallel processing capability of the FPGA to develop and produce the Zynq series chips with a multi-core ARM+FPGA structure, which can be well adapted to smart substations. The above requirements of various automa...

AI Technical Summary

Problems solved by technology

In SMP (Symmetrical Multi-Processing, Symmetrical Multi-Processing) mode, this problem is usually handed over to the operating system. The general implementation method is that the bottom layer of the system maintains a peripheral buffer, and the application uses virtual peripherals. Unified output after cache transmission; in AMP mode, if this method is adopted, the data processing efficiency will be greatly reduced, and the meaning of adopting AMP mode will be lost

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