A kind of semiconductor device and its manufacturing method and electronic device

Abstract

The invention provides a semiconductor apparatus, a manufacturing method of the semiconductor apparatus and an electronic device. The manufacturing method of the semiconductor apparatus comprises steps of providing a front end apparatus including the semiconductor substrate, a first grid and a second grid located on the semiconductor substrate, wherein the width of the first grid is more than the width of the second grid; forming a hard mask layer on the first grid; forming bottom anti-reflective coatings on the first grid, the second grid and the semiconductor substrate; forming photoresist mask layers of the bottom anti-reflective coatings exposed at the upper part of the first grid on the bottom anti-reflective coatings; performing the etching process to remove the bottom anti-reflective coatings uncovered by the photoresist mask layer at the upper part of the first grid and a hard mask layer on the upper part of the first grid; removing the bottom anti-reflective coating and the photoresist mask layer; settling an interlayer dielectric layer. The method effectively avoids residue and disk sunken of silicon nitride on a wide grid; the surface flatness of the interlayer dielectric layer after polishing is good; the apparatus performance and yield are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] Chemical mechanical polishing (CMP) is a processing technology that combines chemical corrosion and mechanical removal, and is mainly used for the planarization of silicon wafers in the semiconductor industry. The effect of surface planarization by CMP is greatly improved compared with the effect of surface planarization by traditional planarization technology, so CMP has become a key planarization technology in the semiconductor industry. [0003] At present, when the size of the semiconductor device is reduced to 28nm or below, the fabrication method of the interlayer dielectric layer (ILD) between polysilicon gates is mostly carried out by fixed abrasive (FA) CMP. At the 28nm scale, the thickness of the hard mask silicon nitride on the wafer before deposition...

AI Technical Summary

Problems solved by technology

It can be seen from the figure that after the stress proximity technique (SPT), ILDCMP using the FA method can obtain less silicon nitride residues and smaller dish-shaped depressions, and better flatness; while ILDCMP using the abrasive slurry There will be more silicon nitride residue and larger dishing, thicker SiN residue thickness on the wider gate area, and poor planarity

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