Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Super-junction device manufacturing method and super-junction device

A superjunction device and epitaxial layer technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as large gate-to-drain capacitance, reduce gate-to-drain capacitance, reduce switching loss, and reduce switching time. Effect

Inactive Publication Date: 2017-01-04
PEKING UNIV FOUNDER GRP CO LTD +1
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The invention provides a method for manufacturing a super-junction device and a super-junction device, which are used to solve the technical problem of large gate-to-drain capacitance of super-junction devices in the prior art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Super-junction device manufacturing method and super-junction device
  • Super-junction device manufacturing method and super-junction device
  • Super-junction device manufacturing method and super-junction device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] Embodiment 1 of the present invention provides a method for manufacturing a super junction device. figure 1 A flow chart of the method for manufacturing a super junction device provided in this embodiment. Such as figure 1 As shown, the method for manufacturing a super junction device in this embodiment may include:

[0044] Step 101 , forming an epitaxial layer 2 on the substrate 1 , and forming an oxide layer mask 4 on the epitaxial layer 2 .

[0045] Specifically, the epitaxial layer 2 in this embodiment can be an N-type epitaxial layer, and the substrate 1 can be an N-type substrate. The method for forming the N-type epitaxial layer and the N-type substrate belongs to the prior art, and is not described in this embodiment. Let me repeat.

[0046] The method provided in this embodiment, after forming the epitaxial layer 2 on the substrate 1 and before forming the oxide layer mask 4 on the epitaxial layer 2, may further include: forming a super junction P column in...

Embodiment 2

[0060] Embodiment 2 of the present invention provides a super junction device. For the super device provided in this embodiment, please refer to Figure 10 . Such as Figure 10 As shown, the super junction device in this embodiment may include: a substrate 1, an epitaxial layer 2 formed on the substrate 1, an oxide layer 6, and a gate oxide layer formed on the oxide layer 6 9, and a polysilicon gate 10 formed on the gate oxide layer 9;

[0061] Wherein, the epitaxial layer 2 is provided with a groove 5 , the oxide layer 6 is located in the groove 5 , and the oxide layer 6 is flush with the top of the epitaxial layer 2 .

[0062] Specifically, the epitaxial layer 2 may be an N-type epitaxial layer. Correspondingly, the super-junction device in this embodiment may further include: a super-junction P-column structure 3 formed in the epitaxial layer 2, a P-type body Region 7, N-type source region 8, and dielectric layer 11 and metal layer 12 formed on the polysilicon gate 10. ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a super-junction device manufacturing method and a super-junction device. The method comprises the following steps of forming an epitaxial layer on a substrate and forming an oxide layer mask film on the epitaxial layer; carrying out photoetching and etching on the oxide layer mask film, and under masking of the oxide layer mask film, etching a groove on the epitaxial layer; forming an oxide layer in the groove, and using surface planarization processing so that the oxide layer is flushed with a top of the epitaxial layer; forming a gate oxide layer and a polysilicon gate above the oxide layer. By using the super-junction device manufacturing method and the super-junction device, the groove is formed on the epitaxial layer and the oxide layer is formed in the groove so that a gate-drain capacitance can be effectively reduced, switch time of the device is decreased and switch losses of the device are reduced. Compared to the prior art, by using the method and the device of the invention, a thickness of the gate oxide layer is not increased and dynamic performance of the device is not influenced.

Description

technical field [0001] The invention relates to integrated circuit manufacturing technology, in particular to a method for manufacturing a super junction device and a super junction device. Background technique [0002] The drain and source poles of the superjunction device are located on both sides of the device, and the current flows vertically inside the device during operation, which increases the current density, improves the rated current, and the on-resistance per unit area is also small. It is a very useful Wide range of power devices. [0003] Operating loss is the most important performance parameter of super junction devices, which can be divided into three parts: conduction loss, cut-off loss and switching loss. The conduction loss is determined by the on-resistance, the cut-off loss is affected by the reverse leakage current, and the switching loss It refers to the loss caused by the charging and discharging of parasitic capacitance during the switching process...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/28H01L29/78
CPCH01L21/28158H01L21/28035H01L29/78
Inventor 赵圣哲
Owner PEKING UNIV FOUNDER GRP CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com